Threshold voltage instability measured by the pulse current-voltage technique has been recognized as the transient charging and discharging of the preexisting bulk traps in Hf-based high-k gate dielectrics, and these high-k traps or called border traps can instantly exchange charge carriers with the underlying Si substrate by tunneling through the thin interfacial oxide. Based on an elastic tunneling model through trapezoidal potential barriers, the spatial and energetic distribution of border traps in the HfO2∕SiO2 high-k gate stack can be profiled as a smoothed, three-dimensional mesh by measuring the low-frequency capacitance-voltage characteristics of high-k metal-oxide-semiconductor capacitors with n-type Si substrate.

A new process for tungsten gate metal oxide semiconductor (MOS) capacitors has been developed using chemical vapor deposition (CVD) of tungsten on a thin poly-Si layer of appropriate thickness. The poly-Si acts as a sacrificial layer and is consumed during the CVD of tungsten (W). This process yields a nearly pure W metal gate after SiH4 reduction of WF6 at 300°C. Compared with sputtered tungsten films, the CVD tungsten film has lower resistivity and lower intrinsic film stress. In addition, the CVD tungsten metal gate MOS capacitor has a lower interface state density (D18) and a higher charge-to-breakdown (Q84), than sputter-deposited tungsten gate MOS capacitors. InfroductionAs device dimensions continue to decrease for higher density and improved performance in integrated circuits, there is a growing demand for more highly conductive gate and interconnection materials. The poly-Si now used for this purpose in conventional processing has certain limitations, due mainly to limited conductivity. In addition, it is well known that the use of p-polygates has become indispensable for p-channel metal oxide semiconductor field effect transistors (MOSFET5) in the deep submicron regime. However; the penetration of boron impurities results in a shift of the threshold voltage, an increase in subthreshold swing and leakage current, and degradation of the gate oxide reliability.1-3 Metal silicides4' have been considered because their conductivities are higher than that of poly-Si by one order of magnitude. Furthermore, it is expected that materials with conductivities higher than those of silicides will be required in the future for very high density integrated circuits. Thngsten is considered a very promising gate material candidate because it makes gate implantation unnecessary. Furthermore, tungsten also provides low resistivity and near midgap work function.7 Tungsten gates have conventionally been prepared by sputtering,8 plasma-or laser-enhanced chemical vapor deposition (CVD).9"° However, conventional CVD of tungsten using silane or hydrogen reduction of WF, cannot deposit W on oxides at temperatures below 400°C. Although tungsten can be forced directly onto Si02 surfaces at temperatures above 400°C, the resulting films possess 3-type structures with high resistivity'2 and tend to peel off because of poor adhesion to the Si02. In this study, we developed a new process, in which CVD of tungsten was employed to deposit W on a thin sacrificial poly-Si layer deposited on a gate oxide prior to CVD of the W itself. The natural self-limiting Si consumption property of the chemical vapor deposition of tungsten,'3 the so-called Si reduction reaction, will cause the thin sacrificial poly-Si layer to be consumed, so that a nearly pure W metal-gate MOS capacitor will result at the low deposition temperature of 300°C. We introduce the first tungsten metal gate Electrochemical Society Active Member.(the poly-Si layer is completely consumed) MOS capacitor with the tungsten-gate formed by CVD process; this differs from conventional ...

This work investigates the characteristics of PtSi-silicided p+n shallow junctions fabricated by implanting BF+2 ions into either the Pt/Si (ITM scheme) or the PtSi/Si (ITS scheme) structure followed by annealing in N2 furnace at temperatures from 650 to 800 °C. For a structure with Pt film of 30 nm thickness or PtSi film of 60 nm thickness, the implantation energy ranges from 40 to 80 keV with a dose ranging from 1×1015 to 1×1016 cm−2. For the ITS samples with BF+2 implantation at 40 keV, all ions are confined in the PtSi layer; therefore, only a modified Schottky junction is formed by the diffusion of boron atoms from the PtSi film during the annealing. The junction depth may be as shallow as 30 nm from the PtSi/Si interface. A complete p+n junction is formed for the ITM samples with implantation at 40 keV as well as all the samples implanted at 80 keV. The junction thus obtained has a forward ideality factor lower than 1.02 and a reverse current density less than 0.2 nA/cm2 at −5 V. Activation energy measurement indicates that most of the implantation damages have been recovered after annealing at a temperature as low as 700 °C. The reverse area and peripheral leakage current density are separated by measuring diodes of different perimeter/area ratio. For good samples, the reverse peripheral current comes from the surface generation current within the depletion region underneath the field oxide. All of the experimental results reveal that either Pt or PtSi film can be employed as an efficient barrier film in the ITM/ITS technique to form excellent and ultrashallow junctions with a low thermal budget.

Ion implantation through metal (ITM) or metal silicide (ITS) appears to be an attractive technique for self-aligned silicided shallow junction formation. Since most of the implanted ions are confined in the barrier film, the damage generated in the silicon substrate is reduced and so is the required post-implant annealing temperature. The purpose of this work is to study the capability of using Pt and PtSi in the ITM/ITS technique. As+ ions were implanted through 30-nm Pt or 60-nm PtSi at 80 keV with doses ranging from 1×1015 to 1×1016 cm−2. The implanted samples were annealed from 650 to 800 °C. Junction depths measured by spreading resistance and secondary-ion mass spectroscopy on 750 °C annealed samples are about 0.11 and 0.13 μm for the ITS and ITM schemes, respectively. The reverse area and peripheral leakage current density (JRA and JRP) are separated by measuring diodes of different size. All samples with a dose of 1×1015 cm−2 failed due to an insufficient amount of dopants which were incorporated into Si. For a dosage greater than 5×1015 cm−2, the JRA at −5 V is less than 0.2 nA/cm2 and the forward ideality factor is lower than 1.02 for the ITS samples annealed at 750 °C. Activation energy measurement shows that the JRA is diffusion-component dominated while the JRP is generation-component dominated at room temperature. Surface generation current and lateral implantation damage-induced current are examined and discussed in detail. A possible reason is that the lateral junction depth is less than the vertical junction depth and the depletion region may be extended to near the PtSi/Si interface. Annealing at 800 °C degrades the junction characteristics because the Pt from PtSi diffuses into the junction region. Based on the experimental results and analysis we conclude that either Pt or PtSi film can be employed as an efficient barrier film in the ITM/ITS technique. A high-quality and ultrashallow junction can be fabricated using furnace annealing at temperature as low as 750 °C. The peripheral current generated at the silicide/silicon interface dominates the reverse junction current and cannot be avoided for the silicided junction with a junction depth less than 50 nm from the interface. This factor acts as a physical limitation as the junction depth scales down.