Massive deployment of wireless autonomous sensor nodes requires their lifetime extension and cost reduction. The analog frontend (AFE) plays a key role in this context. This paper presents a successive approximation register analog-to-digital converter (SAR ADC) with a switched-capacitor programmable gain switched preamplifier (SC PGSA), as a basic component of an integrated ultra-low power AFE. AFE resolution, sample rate and signal gain are configurable between 6 to 13 bit, 1 to 10 kS/s and -6 to 12 dB, respectively. The circuit draws 10.5 µW from a 1.8 V standard supply voltage, achieving an effective number of bits of 12.6 bit and a Walden figure of merit of 169.1 fJ/st. and 30.6 fJ/st., computed with and without preamplifier, respectively. The circuit is employed in a modular internet of things sensor node, suitable to be solely powered from microenergy sources (energy harvesters). In order to feed charge-scaling SAR ADC inputs with the sensor voltages, typically a preamplifier stage is implemented, which can create energy overhead of magnitudes larger than the ADC power. This paper presents a duty-cycled preamplifier with programmable gain for SAR ADCs, utilizing switched-capacitor switched-opamp technique in the SC PGSA. No additional buffer circuitry is needed to charge the SAR ADC, and the preamplifier design is relaxed in power constraint. The circuit targets the low-cost internet of things market. Cost efficiency is achieved by technology choice, wide configurability and shortened ASIC design cycles. The latter results from partly generated layout, easing reuse of circuit parts from a different CMOS node. A testchip in a low-cost 180 nm silicon-on-insulator technology was fabricated.

The Zero-Power Signal Conditioning IP (ZeSCIP) aims to operate in an autonomous environmental sensor node with energy harvester-extended life time. In this application, the sensor analog frontend has to process environmental signals of different nature, while it is confronted with power and space limitations and low operating voltages. In a flexible modular setup, the ZeSCIP analog frontend is attached to commercial sensors, which represent a specific air quality sensing scenario. This multi-sensor module is stacked to an ARM Cortex M4based STM32 Nucleo™ board, creating an operational test setup of a modular sensor node, controlled via USB link. In measurement, the module consumes only 35.5 µW during processing of light, CO gas and temperature sensor signals, which makes it suitable to be autonomously powered by energy harvesters.

The trend towards ubiquitous electronics drives the development of autonomous hardware components with longer operating times. This work presents a novel ultra-low power analog sensor frontend (AFE) for environmental sensing applications. Relevant operation parameters like resolution (6 to 13 bit), sample rate (1 to 7.5 kS/s), voltage gain (−6 to 12 dB), transimpedance (1.5 to 12 M ), and moving average (1 to 128 taps) are real-time programmable. Four input channels are separately configurable to process voltage, current and potentiometric signals of external or internal sources. The flexible channel-wise configuration enables processing of various signal types and therefore offers a versatile solution for sensors from the Internet-of-Things (IoT) market segment. The AFE integrates switched-capacitor amplifiers, 13 bit, 10 kS/s successive approximation analog-to-digital converter (SAR ADC), bias references, oscillator, digital signal pre-processing and communication in a system-on-chip. A novel sensor power regime supports the flexible read-out of commercial IoT sensors, resulting in excellent power consumption. Fabricated samples in 180 nm technology show an ultra-low power consumption of 8.8 µW. The SAR ADC achieves 10.6 effective bits while consuming 1.8 µW, resulting in a Figure-of-Merit of 116.0 fJ/conv.-step. Measurements with commercial sensors prove the AFE's suitability for an energy-harvester-powered IoT environmental sensor node.

We present a 5 MSample/s current steering digitalto-analog converter which has a programmable resolution between 8 bit, 10 bit and 12 bit. A selectable 2-D unary matrix architecture and a resolution programmable decoder are proposed for the resolution programmability. The proposed current steering digital-to-analog converter is implemented in a 22 nm FD-SOI (Fully Depleted Silicon-on-Insulator) CMOS technology. The simulation verifications of the CS-DAC at three resolution modes are made. The maximum DNL of 0.06 LSB is obtained at 8 bit resolution modes, and the maximum INL (Integral Non-Linearity) of 0.53 LSB is obtained at 12 bit resolution modes. The minimum SFDR (Spurious-Free Dynamic Range) of 47.93 dBc is obtained at 8 bit resolution mode.

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