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The trend toward technology ubiquity in human life is constantly increasing and the same tendency is clear in all technologies aimed at human monitoring. In this framework, several smart home system architectures have been presented in literature, realized by combining sensors, home servers, and online platforms. In this paper, a new system architecture suitable for human monitoring based on Wi-Fi connectivity is introduced. The proposed solution lowers costs and implementation burden by using the Internet connection that leans on standard home modem-routers, already present normally in the homes, and reducing the need for range extenders thanks to the long range of the Wi-Fi signal. Since the main drawback of the Wi-Fi implementation is the high energy drain, low power design strategies have been considered to provide each battery-powered sensor with a lifetime suitable for a consumer application. Moreover, in order to consider the higher consumption arising in the case of the Wi-Fi/Internet connectivity loss, dedicated operating cycles have been introduced obtaining an energy savings of up to 91%. Performance was evaluated: in order to validate the use of the system as a hardware platform for behavioral services, an activity profile of a user for two months in a real context has been extracted.

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This work was supported by the project "Biosensoristica innovativa per i test sierologici e molecolari e nuovi dispositivi PoCT per la diagnosi di infezione da SARS-CoV-2" funded in 2020 by "Bando Straordinario di Ateneo per Progetti di Ricerca Biomedica in Ambito SARS-COV-2 e COVID-19" -

Recent research in wearable sensors have led to the development of an advanced platform capable of embedding complex algorithms such as machine learning algorithms, which are known to usually be resource-demanding. To address the need for high computational power, one solution is to design custom hardware platforms dedicated to the specific application by exploiting, for example, Field Programmable Gate Array (FPGA). Recently, model-based techniques and automatic code generation have been introduced in FPGA design. In this paper, a new model-based floating-point accumulation circuit is presented. The architecture is based on the state-of-the-art delayed buffering algorithm. This circuit was conceived to be exploited in order to compute the kernel function of a support vector machine. The implementation of the proposed model was carried out in Simulink, and simulation results showed that it had better performance in terms of speed and occupied area when compared to other solutions. To better evaluate its figure, a practical case of a polynomial kernel function was considered. Simulink and VHDL post-implementation timing simulations and measurements on FPGA confirmed the good results of the stand-alone accumulator.