In this paper, we present on-silicon structures onwafer measurements up to 500 GHz and a comprehensive electromagnetic (EM) simulation analysis to understand nonideal behaviour in the measured data. The EM simulations are performed in such a way that the simulation setup remains very close to the physical measurement environment where a faithful true EM model of the RF probes is an essential requirement. In this process, four different RF probes used during measurements in the frequency bands 1 GHz-110 GHz, 140 GHz-220 GHz, 220 GHz-325 GHz and 325 GHz-500 GHz are designed in the EM simulator. We also highlight the importance of the frequency band specific probe models to develop a deep understanding of the problems encountered in the sub-THz and THz measurements.

THz silicon based electronics is undergoing rapid developments. In order to keep this momentum high, an accurate and optimized on-wafer characterization procedure needs to be developed. While evaluating passive elements, the measured sparameter data can be verified by a direct use of EM simulation tools. However, this verification requires to precisely introduce part of the measurement environment such as the probes, the pads and access lines to accurately predict the impact of calibration and layout for on-wafer measurements. Unfortunately, this procedure is limited to passive elements. Hence, in this work, we propose a new procedure to emulate the measurement of active devices using an electromagnetic-SPICE co-simulation. By this method, one can clearly highlight that a measurement artefact that was observed for the transistor measurement can be reproduced. One of the most representative example of measurement artefact involves the measurement and estimation of fMAX which is not constant over all frequency band. Also the measurement is difficult to perform above 40 GHz. This typical problem is now undoubtedly attributed to the probe-to-substrate coupling and probe-to-probe coupling which are strongly dependent on the probe geometry. Finally, this co-simulation procedure evidently underlines the need for an optimized de-embedding procedure above 200 GHz.

In this paper, we present on-wafer TRL-calibrated measurements of silicon test structures fabricated using STMicroelectronics' B55 technology up to 500 GHz. The structures are fabricated in two subsequent runs and the respective structure in each run has a different design. The improvements in the test structures layout design are presented on the terminal capacitances of "open-M1", which is an important test structure for the de-embedding of the transistor accesses. The improvements are examined using HFSS electromagnetic (EM) simulations, including the RF probe models and the neighboring structures.