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This paper is focused on the automated synthesis of slow-wave structures based on microstrip lines loaded with patch capacitors. Thanks to the presence of the shunt capacitors, the effective capacitance of the line is enhanced, and the phase velocity of the structure can be made significantly smaller than the one of the unloaded line. The target is to achieve the layout of the slow-wave structure able to provide the required slow-wave ratio, characteristic (Bloch) impedance and electrical length (i.e., the usual specifications in the design of slow-wave transmission lines). To this end, a two-step synthesis method, based on the aggressive space mapping (ASM) algorithm, is proposed for the first time. Through the first ASM algorithm, the circuit schematic providing the target specifications is determined. Then, the second ASM optimizer is used to generate the layout of the structure. In order to illustrate the potential of the proposed synthesis method, three application examples are successfully reported. The two-step ASM algorithm is able to provide the layout of the considered structures from the required specifications, without the need of an external aid in the process.

This paper is focused on the application of space mapping optimization to the automated synthesis of transmission lines loaded with complementary split ring resonators (CSRRs) and open complementary split ring resonators (OCSRRs). These structures are of interest for the implementation of resonant-type metamaterial transmission lines, and for the design of planar microwave circuits based on such complementary resonators. The paper presents a method to generate the layouts of CSRR-and OCSRRloaded microstrip lines from the elements of their equivalent circuit models. Using the so-called aggressive space mapping (ASM), a specific implementation that uses quasi-Newton type iteration, we have developed synthesis algorithms that are able to provide the topology of these CSRR-and OCSRR-loaded lines in few steps. The most relevant aspect, however, is that this synthesis process is completely automatic, i.e., it does not require any action from the designers, other than initiate the algorithm. Moreover, this technique can be translated to other electrically small planar elements described by lumped element equivalent circuit models.

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