The design of low consumption CMOS circuits, nanotechnologies and quantum computing has becomed more attached to the reversible logic. A set of gates have been recently exploited in reversible computer science for the design of certain circuits. Among them, we find the decoders. In this paper we have exploited a recent study making the design of the decoder 2 to 4, 3 to 8, and n to 2 n , our work aims to enhance the previous designs , by replacing some reversible gates by others while maintaining their functionality and improving their performance criteria namely the number of gates (CG), number of garbage outputs (NGO), number of constant inputs(NCI), Quantum cost (QC) and hardware complexity (HC), compared to our study of the base and other recent studies from which we have obtained remarkable results.

The field of quantum computing, reversible logic, and nanotechnology have earned much attention from researchers in recent years due to their low power dissipation. Quantum computing has been a guiding light for nanotechnology, optical computing of information, low power CMOS design, computer science. Moreover, the dissipation of energy in the field combinatorial logic circuits becomes one of the most important aspects to be avoided. This problem is remedied by a reversible logic favoring the reproduction of inputs to outputs, which is due to the absence of unused bits. Every bit of information not used generates a loss of information causing a loss of energy under the form of heat, the reversible logic leads to zero heat dissipation. Among the components affected by reversible logic are binary reversible counter and converter from decimal to BCD encoder(D2BE) which are considered essential elements. This article will propose an optimized reversible design of a converter from decimal to BCD encoder (D2BE) and an optimized design of reversible Binary counter with up/ down. Our designs show an improvement compared to previous works by replacing some reversible gates with others while keeping the same functionality and improving performance criteria in terms of the number of gates, garbage outputs, constant inputs, quantum cost, delay, and Hardware complexity.