Abstract-The appearance of radix-2 2 was a milestone in the design of pipelined FFT hardware architectures. Later, radix-2 2

Abstract-This paper presents a new pipelined hardware architecture for the computation of the real-valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency.The architecture is based on a novel algorithm for the computation of the RFFT, which, contrary to previous approaches, presents a regular geometry suitable for the implementation of hardware structures. Moreover, the algorithm can be used for both the Decimation In Time (DIT) and Decimation In Frequency (DIF) decompositions of the RFFT and requires the lowest number of operations reported for radix 2.Finally, as in previous works, when calculating the RFFT the output samples are obtained in a different order. The problem of reordering these samples is solved in this paper and a pipelined circuit that performs this reordering is proposed.

This paper presents a novel pipelined architecture to compute the fast Fourier transform of real input signals in a serial manner, i.e., one sample is processed per cycle. The proposed architecture, referred to as Real-valued Serial Commutator, achieves full hardware utilization by mapping each stage of the FFT to a half-butterfly operation that operates on real input signals. Prior serial architectures to compute FFT of real signals only achieved 50% hardware utilization. Novel dataexchange and data-reordering circuits are also presented. The complete serial commutator architecture requires 2 log 2 N − 2 real adders, log 2 N − 2 real multipliers and N + 9 log 2 N − 19 real delay elements, where N represents the size of the FFT.

Abstract-This paper presents a new approach to design multiplierless constant rotators. The approach is based on a combined coefficient selection and shift-and-add implementation (CCSSI) for the design of the rotators. First, complete freedom is given to the selection of the coefficients, i.e., no constraints to the coefficients are set in advance and all the alternatives are taken into account. Second, the shift-and-add implementation uses advanced single constant multiplication (SCM) and multiple constant multiplication (MCM) techniques that lead to lowcomplexity multiplierless implementations. Third, the design of the rotators is done by a joint optimization of the coefficient selection and shift-and-add implementation. As a result, the CCSSI provides an extended design space that offers a larger number of alternatives with respect to previous works. Furthermore, the design space is explored in a simple and efficient way.The proposed approach has wide applications in numerous hardware scenarios. This includes rotations by single or multiple angles, rotators in single or multiple branches, and different scaling of the outputs.Experimental results for various scenarios are provided. In all of them, the proposed approach achieves significant improvements with respect to state of the art.

This paper presents an in-depth study, implementation, and validation of Fast Fourier Transform Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to get faster real time in broadband digital receivers. To support the signal processing designer when implementing this kind of systems on FPGA platforms we have developed a design space exploration tool for FFT architectures.