No abstract

International audienceRigorous system design requires the use of a single powerful component framework allowing the representation of the designed system at different levels of detail, from application software to its implementation. The use of a single framework allows to maintain the overall coherency and correctness by comparing different architectural solutions and their properties. In this paper, we present the BIP (Behavior, Interaction, Priority) component framework which encompasses an expressive notion of composition for heterogeneous components by combining interactions and priorities. This allows description at different levels of abstraction from application software to mixed hardware/software systems. Then, we introduce a rigorous design flow that uses BIP as a unifying semantic model to derive from an application software, a model of the target architecture and a mapping, a correct implementation. Correctness of implementation is ensured by application of source-to-source transformations in BIP which preserve correctness of essential design properties. The design is fully automated and supported by a toolset including a compiler, the D-Finder verification tool and model transformers. We illustrate the use of BIP as a modeling formalism as well as crucial aspects of the design flow for ensuring correctness, through an autonomous robot case study

We address the problem of verifying programs manipulating one-selector linked data structures. We propose and study in detail an application of counter automata as an accurate abstract model for this problem. We let control states of the counter automata correspond to abstract heap graphs where list segments without sharing are collapsed, and use counters to keep track of the number of elements in these segments. As a significant theoretical result, we show that the obtained counter automata are bisimilar to the original programs. Moreover, from a practical point of view, our translation allows one to apply efficient automatic analysis techniques and tools developed for counter automata (integer programs) in order to verify both safety as well as termination of list-manipulating programs. As another This work is a full and revised version of the extended abstract [10] published in Proceedings of CAV'06. Form Methods Syst Des (2011) 38: 158-192 159 theoretical contribution, we prove that if the control of the generated counter automata does not contain nested loops (i.e., these automata are flat), both safety and termination are decidable for the original programs. Subsequently, we generalise our counter-automata-based model to keep track of ordering properties over lists storing ordered data. Finally, we show effectiveness of our approach by verifying automatically safety as well as termination of several sorting programs.

is a software tool aiming at assisting designers of real-time systems to develop projects meeting the speci ed requirements. One major objective of Kronos is to provide a veri cation engine to be integrated into design environments for real-time systems in a wide range of application areas. Real-time communication protocols 8,10], timed asynchronous circuits 16,4], and hybrid systems 18,10] are some examples of application domains where Kronos has already been used. Kronos has been also used in analyzing real-time systems modeled in several other process description formalisms, such as Atp 17], Aorta 5], Et-lotos 8], and T-argos 15]. On the other direction, the tool itself provides an interface to untimed formalisms such as labeled-transition systems (LTS) which has been used to exploit untimed veri cation techniques 20]. Theoretical background The system-description language of Kronos is the model of timed automata 2], which are communicating nite-state machines extended with continuous realvalued variables (clocks) used to measure time delays. Usually a system is modeled as a network of automata. Communication is achieved by label synchronization a la CCS or CSP (binary or n-ary rendezvous), or shared variables (of bounded integer or enumeration type). System requirements can be speci ed in Kronos using a variety of formalisms, such as the real-time logic Tctl 1,14], timed B uchi automata, or ? Kronos is developed at Verimag, a joint laboratory of UJF, Ensimag and CNRS.