Monolithic multi-junction solar cells made on active silicon substrates are a promising pathway for low-cost highefficiency devices. We present results of GaInP/GaAs/Si triplejunction solar cells, fabricated by direct growth on silicon in an MOVPE reactor using a GaAs y P 1-y buffer structure to overcome the lattice mismatch between Si and GaAs. A low temperature (750 °C) Si surface preparation process and a SiN x diffusion barrier at the rear side have been implemented to maintain the minority carrier lifetime in the Si bottom cell. Conversion efficiencies up to 19.7 % have been achieved under AM 1.5g spectral conditions. The cells are compared to identical GaInP/GaAs dual-junction solar cells grown on bulk GaP and GaAs substrates to identify loss mechanisms. Subcell electrical characterization using electroluminescence reveals a significant voltage loss of the III-V subcells on Si, compared to the same structures grown on GaP or GaAs. Electron channeling contrast imaging of the metamorphic GaAs y P 1-y buffer shows a three times higher threading dislocation density on Si (1.4×10 8 cm -2 ) than on GaP substrates, and atomic force microscopy shows holes in the GaAs y P 1-y buffer on Si that are not observed on GaP. Approaches to reach lower defect densities for the III-V layers on silicon are discussed.
III-V on Si multijunction solar cells exceede the efficiency limit of Si singlejunction devices but are often challenged by expensive layer transfer techniques. Here, progress in the development of direct epitaxial growth for GaInP/GaAs/Si triple-junction solar cells is reported. III-V absorbers with a total thickness of 4.9 μm are grown onto a Si bottom cell using metal organic vapor phase epitaxy. A new record efficiency of 22.3% under AM1.5g conditions is reached herein, outperforming the previous value of 19.7%. This improvement is possible through better nucleation conditions for the first GaP layer on Si and consequently the reduction of threading dislocations within the III-V absorbers from 1.4 Â 10 8 to 2.2 Â 10 7 cm À2 . Further efficiency improvements toward 30% require even lower threading dislocation densities in the order of 1 Â 10 6 cm À2 , better light trapping in the Si bottom cell, and a reduction of parasitic absorption within the GaAs y P 1-y graded buffer.
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