Increasing demands regarding complexity and time-to-market of embedded systems raise the necessity to continuously explore new development flows and introduce new tools in order to survive as one of the leading semiconductor and system suppliers in the market. This document shall outline an innovative development approach that was chosen at Infincon Technologies AG to mainly pull-in and safeguard the development and verification of the embedded firmware part of a complex signal processing device for mobile applications. I. MOTIVATIONIn the wireless market it is no longer sufficient to deliver a piece of HW only. Mobile cell phone manufactures do expect a completely verified and certified reference design including software such as applications, protocol stacks, etc. Therefore existing design flows have to be adapted to address the HW/SW co-design needs.Nonetheless, in such projects major challenges remain: The permanently increasing amount of software, the need to implement more and more highly timing-critical applications and less time to get a product out into the market.II. DEVELOPMENT APPROACHES To be able to fulfill the requirements above a new approach had to be chosen for the development and verification of the embedded firmware part of a complex communication device at Infineon Technologies AG.Previously such developments were mainly based on FPGA prototypes. Obviously those cannot be created before the HW development has reached a state where a stable netlist is available. Due to their significant gate count it has become increasingly difficult to map complex communication devices onto one or even more FPGAs while still meeting all required timing constraints. Hence, with such a classical approach it would not have been possible to meet the demanding requirements regarding firmware availability and quality. Therefore a FPGA was no longer considered but an alternative methodology was chosen.The key element of the new development approach is a Virtual System Prototype (VSP) that reflects the silicon in a sufficient detailed level and allows acceptable simulation speeds using state-of-the-art peripheral models and simulators. The VSP has been built by using a combination of the tool-vendor's processor and peripheral models and additional, proprietary SystemC models. The detail level of the models has been chosen such that the VSP is still a cycleaccurate image of the hardware design when looking at it from a firmware perspective. All functionality that is invisible to the FW has been abstracted as much as possible to increase the overall simulation speed. A C++/SystemC test bench has been added to the VSP that is able to execute complex test cases also written in C++.Wherever applicable, the SystemC peripherals have been enhanced by so-called "slave simulations", where existing and newly designed algorithm models were embedded into a SystemC wrapper and thus could be made part of the VSP environment. This yields a high reuse of the results of the algorithm exploration and a close coupling of the real RTL de...

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