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This paper describes a new coding scheme and its CMOS implementation for field powered RF IC tag systems. The main feature of the new scheme is that it does not require PLL for clock recovery and decoding process, and the coding signal produced has 50% duty cycle and contains both clock and data. Also the clock signal generated by the decoder adopting the scheme drives circuit at proper time to achieve maxitnal power efficiency. A test chip has been fabricated with a 0.8 pm standard CMOS process. The evaluation test board with this chip operates with I mW RF signals and no battery. IntroductionContactless IC tag systems are suitable for rcducing the time for assortment and improving the security in distribution service systems or FA systems. Figure I shows basic block diagram of the contactless IC tag. It consists of several blocks: an antenna, rectifying diodes for DC power generation and data detection, input amplifier, data recovery circuit, controller memories, and transmitting driver. A readedwriter transmits amplitude modulated signal containing data and clock to the tag. When the tag receives "High" signal, the capacitor at power line is charged. After the tag generates DC power and detects the signal, the data and clock are decoded from the detected signal. The tag modulates its antenna impedance with the transmitting driver to answer to the reader/wri ter.In the previous work for RF IC tag system [ I]. Manchester code [2] has been used, which requires a PLL with VCO for clock recovery and decoding. In this paper, however, to avoid complicated biasing circuit for reducing voltage, process and temperature variation of VCO, a new coding scheme which has constant period between every rising edge of the signals and dose not require VCO for clock recovery is proposed. The decoder for this scheme requires only a RC filter and some

A B S m C TWe have developed the low supply volfuge Voltage Controlled SAW Oscdlator(VCS0) for high-speed optical communicahon equipment A one-port quartz SAW resonator is used to minimize the temperature drifl. We use a varactor and a serial inductor to get the wide p u h g fiequency range. The total kequency stability less than 2 looppm is achieved, and the p u h g fiequency range is greater than I25Oppm Its volume is 8.5mm hgh, 31mm wide, and 28mm long.We also developed the PLL module using ths VCSO, T~I S module generates the 155.52MHz sme wave signal which is synchronized to the input 19.44MHz signal. The custom PLL LSI is used to achieved the small size and low power consumphon. The pull in range is greater than +-100ppm. Its volume is SSmm high, 41mm wide and long. The Figure 1 shows the external kiew of the VCSO and the PLL module.The miniature coaxial connector is used for the oscdlator output, and small pin-terminals are used for the other connection.