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Bias-stress effects in solution-processed, 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-10) field effect transistors (FETs) are studied under negative and positive direct current bias. The bottom gate, bottom contact polycrystalline Ph-BTBT-10 FET with a hybrid gate dielectric of polystyrene and SiO2 shows high field effect mobility as well as a steep subthreshold slope when fabricated with a highly ordered smectic E liquid crystalline (SmE) film as a precursor. Negative gate bias-stress causes negative threshold voltage shift (ΔVth) for Ph-BTBT-10 FET in ambient air, but ΔVth rapidly decreases as the gate bias decreases and approaches to near zero when the gate bias goes down to 9 V in amplitude. In contrast, positive gate bias-stress causes negligible ΔVth even with a relatively high bias voltage. These results conclude that Ph-BTBT-10 FET has excellent bias-stress stability in ambient air in the range of low to moderate operating voltages.

Thin film transistors (TFTs) have been developed on quartz substrates by using large-grain-size polycrystalline silicon (poly-Si) films. The poly-Si films were fabricated by solid phase crystallization (SPC) of amorphous silicon (a-Si) deposited by plasma-enhanced chemical vapor deposition (PECVD). We have found that the dehydrogenation process is strongly correlated with the SPC of the a-Si, especially in nucleus generation time. The n-channel TFT mobility of 158 cm2/(V ·s) is obtained by using the SPC of the PECVD a-Si.

This paper discusses electrical characteristics and trap-state density in polycrystalline silicon (poly-Si) used in bottom-gate poly-Si thin film transistors (TFTs) processed with high-pressure water vapor annealing (HWA). The threshold voltage uniformity of the HWA-processed TFTs is improved by 42% for N-channel and 38% for P-channel TFTs in terms of standard deviation, and carrier mobility is enhanced by 10% or greater for both N- and P-channel TFTs than those TFTs processed conventionally. Subthreshold swing is also improved by HWA, showing that HWA postannealing is effective for improving the Si/SiO2 interface of the bottom-gate TFTs. Two types of TFTs having different poly-Si crystallinities are examined to investigate carrier transport in poly-Si processed by HWA postannealing. The evaluation of trap-state density for the two types of poly-Si reveals that HWA postannealing is more efficient for N-channel than for P-channel TFTs. Furthermore, HWA postannealing is more effective for poly-Si with high crystallinity to improve TFT characteristics. The analysis of the trap-state distributions and the activation energy of TFT drain current indicate that HWA deactivates dangling bonds highly localized at poly-Si grain boundaries (GBs). Thus, HWA postannealing effects can be interpreted by a GB barrier potential model similar to that applied to conventional hydrogenation.

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