Iron was diffused from a spin-on glass film into n-type GaAs wafers at temperatures of 700~176The observed diffusion depths can be explained by a model with exhaustible diffusion sources. The diffusion coefficient of iron in GaAs has been estimated to be 1 x l0 s exp (-2.7/kT) in this temperature range. The resistivity of the diffused layer was in the order of 104 fl cm. The activation energy of the introduced levels was 0.53 eV for the diffusion at 700 ~ and 800~ which agrees well with the acceptor level of iron. The current-voltage characteristics of mesa diodes made of the diffused wafers showed no excess leakage current, which ensures that high-resistivity, p-type, iron-diffused regions can be used for junction isolation in GaAs integrated circuits.

Amorphous silicon films have been prepared through mercury-photosensitized decomposition of monosilane gas at low temperatures. The films show optical and electrical properties comparable with those of the best films prepared by plasma chemical vapor deposition. The feasibility of amorphous solar cells with short-circuit current densities of more than 10 mA/cm2 has been demonstrated by fabrication of a Schottky barrier structure.

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This paper describes the advantages of an EB Lithographic system using an FE electron gun and steered-beam vector scan to fabricate submicron patterns. Application of this system to submicron pattern writing is studied through exposure intensity distribution (EID) and exposure dosage for submicron patterns. The system can carry out submicron pattern writing with high resolution and small proximity effect. For example, the system provides submicron resist patters with line width larger than 0.5 µm and gap spacing 1.0 µm without proximity effect correction. The application of this system to VLSI submicron pattern writing is also demonstrated.

Integrated circuits, including Hall effect devices, have great potential application in various fields due to their ability to sense magnetic signals and process the signals on a chip (1). One of the most important parameters of Si IC Hall devices has been the offset voltage which appears at the Hall electrodes in the absence of a magnetic field. Although the offset voltage due to geometrical deviations is minimized by the IC technique, the offset voltage is seriously affected by mechanical streRs during packaging. Therefore, design of Si Hall ICs should take the stress dependence of the offset voltage into account.In a previous paper (2). the. mechanical stress effect of the offset voltages waB studied by the present authors. A model of this effect was proposed and verified by experiments. The model is a square-type bridge circuit consisting of four stress variable resistances (Fig. 1). The maximum offset voltage is expressed a s a function of stress and is given bywhere s and ' 15 a r e the longitudinal and transverse piezoresistance coefficients parallel to one side of the bridge, X is the stress applied, V is the supplied voltage, and w and 1 are the width and length of the Hall device. The Hall voltage V Fig. 1. Hall device and square-type bridge circuit model for the stress dependence of the offset voltage 1 t S is given by H 1) Hamamatau, 431-31 Japan.2) Kokubunji, Tokyo. 186 Japan.