We achieved a reduction in the misregistration of overlying patterns printed on a flexible plastic film and a drastically shorter processing time with fully printed thin-film transistor (TFT) fabrication. This was achieved using a newly developed wet-on-wet (WoW) printing process wherein a subsequent layer can be printed on a previous semi-dried (not-sintered) layer. In the WoW process, as examined by rheological measurements, a semi-dried (highly solidified) state of ink was attained before transferring by utilizing the solvent uptake of a PDMS blanket in offset printing to ensure the structural integrity of the ink layer, and to reduce the inter-contamination of adjoining layers. Loss-on-drying tests and resistivity measurements indicated that molecular penetration at the boundary of adjoining layers with a length of c.a. 70 nm occurred in the WoW process; however, with thicker electrodes, we successfully fabricated a WoW-processed TFT whose performance was comparable with a TFT formed by a conventional printing process.

We have developed a new printing method based on microcontact printing, where an image of dried ink is transferred from a stamp to a substrate via two steps. Combination of two-dimensional press and one-dimensional press enables high resolution printing on a large area using silver nanoparticle ink and poly(3-hexylthiophene) ink. A channel length below 10 mm was successfully obtained. Furthermore, we have succeeded in fabricating organic thin-film-transistor arrays with large area and high precision, 150 mm square area and 200 ppi, respectively, entirely by solution and printing processes.

We developed a novel offset-printing process that permits the fabrication of silver-nanoparticle electrodes embedded in a dielectric layer. We succeeded in embedding approximately 1 µm thick silver electrodes to a dielectric layer with thickness ratio of 1:1.4. The surface-height difference between the embedded electrode and the surrounded dielectric layer was less than 80 nm. By virtue of the surface uniformity of this embedding process, the interconnect breakage of orthogonal wires printed on top of the underlying wire was drastically reduced to 4%, compared to 41% for non-embedded wires. The electric conductivity of embedded electrodes with thickness ≈110 nm was about 10 µΩ cm−1, which was comparable to that of a silver pattern formed on a glass substrate alone. We also examined the characteristics of fully printed thin-film transistors composed of the embedded electrodes, and measured an average mobility of 0.07 cm2 V−1s−1. These results demonstrate the applicability of the proposed technique to the fabrication of printed circuits and devices including active elements.

We developed printed electronics compatible planographic printing methods that enable single-micrometer-order patterning with high rectangularity and thickness uniformity. Instead of conventional planographic printing methods where selective wetting is used for pattern generation, an adhesive latent image produced on a silicone surface is exploited for patterning in the proposed printing methodologies. We further investigated the fundamental mechanisms of the proposed methods by focusing on adhesion contrasts between the blanket, printing area, and non-printing area of a printing plate (PP) and determined that printing is feasible when a simple magnitude relation of adhesions is satisfied for thin layers of size ranging from approximately 50 nm to 100 nm. Latent image formation can be carried out via a simple ultraviolet exposure of the silicone surface, thereby enabling the rapid prototyping of printed device fabrications. The easily preparable, single material-based flat PPs developed in this study have the advantages of flexibility in pattern designs, washing process, fabrication cost, and pattern-rewriting capability compared with the conventional printing methods in which raised surfaces such as stamps or clichés are required for patterning.