Three-dimensional integration of electronics and/or MEMS-based transducers is an emerging technology that vertically interconnects stacked dies with through-silicon vias (TSVs). They enable the realization of circuits with shorter signal path lengths, smaller packages and lower parasitic capacitances, which results in higher performance and lower costs. This paper presents a novel technique for fabricating TSVs from bonded gold wires. The wires are embedded in a polymer, which acts both as an electrical insulator, resulting in low capacitive coupling toward the substrate and as a buffer for thermo-mechanical stress.

Hierarchical models from physical to system-level are proposed for architectural exploration of high-performance silicon systems to quantify the performance and cost trade offs for 2-D and 3-D IC implementations. We show that 3-D systems can reduce interconnect delay and energy by up to an order of magnitude over 2-D, with an increase of 20-30% in performance-per-watt for every doubling of stack height. Contrary to previous analysis, the improved energy efficiency is achievable at a favorable cost. The models are packaged as a standalone tool and can provide fast estimation of coarse-grain performance and cost limitations for a variety of processing systems to be used at the early chip-planning phase of the design cycle.

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