As the technology nodes in integrated circuit (IC) fabrication continue to approach molecular dimensions, the defectivity and planarization provided by conventional chemical mechanical planarization (CMP) processes are no longer sufficient. Therefore, it is necessary to develop new chemistries and innovative screening techniques to solve difficult CMP challenges, including the use of new materials such as cobalt in advanced IC fabrication. For advanced nodes at 14 nm and below, cobalt is currently being implemented on top of Ta/TaN barrier layers and below the copper seeds for the first few metal lines, due to its better conformational coverage within high aspect ratio features and good adhesion to copper. In addition, replacing copper with cobalt in the trenches of interconnect lines for the first few metal layers in the BEOL has demonstrated lower resistivity at smaller dimensions, therefore cobalt interconnects are being considered for < 10 nm nodes for M1 and M2. All these new integration schemes require CMP to achieve planarity with requirements such as low dishing, defectivity, roughness, and tunable selectivity depending on the stack. Under CMP conditions, however, cobalt can suffer from corrosion and static-etch issues, especially when in contact with copper (galvanic corrosion), due to the lower standard reduction potential of cobalt in aqueous solutions across a broad pH range. The corrosion issues must be solved in CMP slurries that deal with cobalt processes (both liner and bulk/plug) to successfully commercialize cobalt-based IC design for next generation semiconductor manufacturing. In this poster, we will discuss the results and learnings from corrosion inhibitor screening techniques such as electrochemical, static-etch, and quartz crystal microbalance (QCM) studies and their correlation with polishing results for developing cobalt slurry formulation platforms. Furthermore, fundamental understanding on the effects of pH and slurry components such as complexors/oxidizers/corrosion inhibitors on the corrosion and removal rate behavior of cobalt films will be discussed.

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Highly selective 2 nd step copper slurries developed by Rodel have efficient barrier (TaN) polishing rates at extremely low down force (1000 Å/min at one psi, and 2000 Å/min at 3 psi). Removal rates of dielectrics (TEOS or low k CDO) can be independently adjusted from zero to nearly any designed value and copper removal rates can be independently controlled from 20 to 500 Å /min, while maintaining the high barrier removal rates. In addition, zero loss of low-k dielectric capping layers has been demonstrated, and zero loss of high metal density (90%) domain of pattern wafers with 30 seconds overpolishing has been demonstrated. Experiments also show that the high selectivity is a true CMP effect and not due to static etching. IntroductionCopper (Cu) chemical mechanical polishing (CMP) employs a two-step polishing process. A first step Cu slurry is used to remove both the bulk copper film layer and any remaining Cu residue on a wafer. The second step CMP process employs slurry that is used for removal of the barrier film, such as tantalum (Ta) or tantalum nitride (TaN). Both slurries are designed to minimize dishing and erosion.

In advanced nodes at 10 nm and below, cobalt (Co) metal is under investigation to replace copper (Cu) in metal lines and vias in back end of line (BEOL) for the first few metal layers due to its better electromigration performance, lower resistivity, conformal coverage in high aspect ratio features, and overall improved device performance. These new integration schemes require Co chemical mechanical planarization (CMP) steps to achieve planarity and desired target thickness. However, Co metal is prone to corrosion in aqueous solutions and its lower redox potential makes it an easy galvanic corrosion target under CMP conditions. Commercial Cu bulk slurries are not compatible for Co polishing as they show significant corrosion defects such as pitting, rough surface, and missing lines after CMP. Advanced Co bulk CMP slurries, therefore, need to contain effective chelator, corrosion inhibitor, and additives at suitable slurry pH to eliminate corrosion defects, while still delivering high Co removal rates (2000 to 5000 Å/min). In this presentation, we will discuss the systematic approach taken to develop a Co bulk CMP slurry formulation platform that can provide high removal rates and low/no corrosion, through development of fundamental understanding of Co surface chemistry, chelation, and corrosion properties. Results and key learnings from the extensive screening techniques such as Tafel polarization, galvanic corrosion, static-etch corrosion, quartz crystal microbalance, and X-ray photo electron spectroscopy analyses used to identify the ideal slurry pH, effective chelators, and corrosion inhibitors will be shared. In addition, Co blanket and pattern wafer polishing performances will be presented for the leading slurry formulations.

As the electronics industry reaches the limits of lithographic processing at sub-10nm dimensions, alternate approaches to meet the demand for increasing device density, reducing package size and improving device performance are being explored. Die stacking approaches to reduce the path length between CPU, GPU and memory devices using a heterogeneous 3DIC chip stacking technology have recently been announced, while memory manufacturers have been creating HBM die stacks for use in servers and highspeed applications. At DuPont Electronics & Imaging (E&I), we have been working to enable 3DIC technology through the development of chemicals and processes such as CMP pads and slurries for polishing all the critical materials, chemical cleaners to remove residues, and photoresists to pattern TSVs, pads and pillars. In addition to these materials, E&I also provides permanent materials for hybrid bonding, including electrodeposited copper for TSVs, pads and pillars as well as tin-silver for pillar capping. Another critical part of hybrid bonding is the adhesive bonding material, which needs to be planarized and yet still have sufficient flow to bond at the same time as the Cu-Cu or Cu-SnAg interconnect. This paper will demonstrate how these critical materials can be used together to fabricate 3DIC devices using a conventional bonding tool. Processing of wafers with sub-20 micron pillars has been completed with good metal joining and void-free bonding of the BCB-based polymer adhesive.