This paper presents improvements in resizing single crystalline Si wafers by using the dicing technology "Thermal Laser Separation" (TLS). Results of this work support the general need to resize wafers to smaller diameters and will play an important role during the transition to larger wafer diameters as currently projected in the ITRS for 450 mm: Wafers of new sizes have to be easily adapted to fit, e.g., currently available metrology tools. TLS process parameters were developed for resizing Si wafers and to produce demo wafers which were analyzed and compared with current state of the art techniques plasma etching, laser ablation and mechanical wafer sawing. For the first time, circular cuts with diameters up to 300 mm were produced out of 450 mm ( thickness: 925 mu m) single crystalline Si wafers with TLS. The TLS process results in two important benefits for resized wafers: First, the edge of the new wafer is of higher quality than the edges produced by state of the art resizing techniques. Second, the TLS process is up to 24 times faster than known resizing processes

Continuously increasing complexity of semiconductor manufacturing processes drives the need for wafer to wafer and even within wafer control loops metrology. Applying Virtual Metrology (VM) techniques is one promising approach to reduce the time between process, measurement and corrective actions. Prior to implementation -besides technical aspects like testing -the investment into VM has to be assessed and justified on the basis of reliable and reasonable data. This paper presents the investment assessment for implementing VM algorithms into plasma etcher tools of a model semiconductor fabrication line. Core of the investment calculation is a spreadsheet-based calculation which allows for a results per quarter evaluation. A Discrete Event Simulation (DES) model was developed to produce relevant input data for the spreadsheet calculation. Potential risks -e.g., delivery of wrong VM results -due to the implementation of VM have been identified and evaluated using the standardized method of Failure Mode and Effects Analysis (FMEA). INTRODUCTION AND MOTIVATIONCurrently, Integrated Device Manufacturers (IDM) face a continuous increase in the complexity of processes as well as the requirements of shorter life cycles and faster ramps. Challenges like these are driven by Moore's Law (Moore 1965) and more recently by the More Than Moore movement. IDMs have to improve equipment and process control to maintain their competitiveness and to keep up with competitors from emerging market countries.

Based on recent progress on laser-based wafer dicing equipment and process, the partners adixen, Fraunhofer IISB and JENOPTIK investigated the use of a vacuum based decontamination process to dry and to decontaminate the substrate surface of the diced wafers from water residuals, which are a side-effect of the TLS (thermal laser separation) approach. The decontamination process was achieved by using an adixen vacuum drying module prototype further to the JENOPTIK TLS dicing process. Within the frame of the European collaborative project SEAL, supported by the European Commission, experimental assessment was conducted by Fraunhofer IISB (research institution) together with JENOPTIK and Adixen.

The silicon carbide (SiC) market is gaining momentum hence productivity in device manufacturing has to be improved. The current transition from 100 mm SiC-wafers to 150 mm SiC-wafers requires novel processes in the front-end as well as the back-end of SiC-chip production. Dicing of fully processed SiC-wafers is becoming a bottleneck process since current state-of-the-art mechanical blade dicing faces heavy tool wear and achieves low throughput due to low feed rates in the range of only a few mm/s. This paper presents latest results of the novel dicing technology Thermal Laser Separation (TLS) applied for separating SiC-JFETs. We demonstrate for the first time that TLS is capable of dicing fully processed 4H-SiC wafers, including back side metal layer stacks, process control monitoring (PCM), and metal structures inside the dicing streets with feed rates up to 200 mm/s. TLS thus paves the way to efficient dicing of 150 mm SiC-wafers.