This paper deals with Automated Test Pattern Generation (ATPG) for large synchronous sequential circuits and describes a new approach based on Simulated Annealing. Simulation-based ATPG tools have several advantages with respect to deterministic and symbolic ones, especially because they can deal with large circuits. A prototypical system named SAARA is used to assess the effectiveness of the Simulated Annealing approach in terms of test quality and CPU time requirements. Results are reported, showing that SAARA is able to deal with large sequential circuits. A comparison with a state-of-the-art ATPG tool based on a Genetic Algorithm shows that SAARA generally improves the attained results in terms of fault coverage.