Ge-nanocrystals (NCs) were synthesized in amorphous TaZrO x by thermal annealing of cosputtered Ge-TaZrO x layers. Formation of spherical shaped Ge-NCs with small variation of size, areal density, and depth distribution was confirmed by high-resolution transmission electron microscopy. The charge storage characteristics of the Ge-NCs were investigated by capacitancevoltage and constant-capacity measurements using metal-insulator-semiconductor structures. Samples with Ge-NCs exhibit a maximum memory window of 5 V by sweeping the bias voltage from À7 V to 7 V and back. Below this maximum, the width of the memory window can be controlled by the bias voltage. The fitted slope of the memory window versus bias voltage characteristics is very close to 1 for samples with one layer Ge-NCs. A second layer Ge-NCs does not result in a second flat stair in the memory window characteristics. Constant-capacity measurements indicate charge storage in trapping centers at the interfaces between the Ge-NCs and the surrounding materials (amorphous matrix/tunneling oxide). Charge loss occurs by thermal detrapping and subsequent band-to-band tunneling. Reference samples without Ge-NCs do not show any memory window. V

Layers of InxGa1−xAs with compositions up to x = 0·4 have been grown on GaAs(001) substrates by molecular beam epitaxy (MBE). The growth process was monitored by RHEED intensity oscillations. The experimental parameters were optimized for growing surfaces with well‐defined compositions in a reproducible manner. The intensity variation of the RHEED oscillations can be described reasonably well using a simple model.

During dynamic random access memory (DRAM) capacitor scaling, a lot of effort was put searching for new material stacks to overcome the scaling limitations of the current material stack, such as leakage and sufficient capacitance. In this study, very promising results for a SrTiO3 based capacitor with a record low capacitance equivalent thickness value of 0.2 nm at target leakage current are presented. Due to the material properties of SrTiO3 films (high vacancy concentration and low band gap), which are leading to an increased leakage current, a physical thickness of at least 8 nm is required at target leakage specifications. However, this physical thickness would not fit into an 18 nm DRAM structure. Therefore, two different new approaches to develop a new ZrO2 based DRAM capacitor stack by changing the inter-layer material from Al2O3 to SrO and the exchange of the top electrode material from TiN to Pt are presented. A combination of these two approaches leads to a capacitance equivalent thickness value of 0.47 nm. Most importantly, the physical thickness of <5 nm for the dielectric stack is in accordance with the target specifications. Detailed evaluation of the leakage current characteristics leads to a capacitor model which allows the prediction of the electrical behavior with thickness scaling.

In this paper our recent research on Ge nanoparticles embedded in ZrO2 will be reviewed. Ge nanoparticles have been deposited by rf-cosputtering of Ge1.6ZrO2/ZrO2 superlattices and subse-quent annealing. TEM measurements confirmed the phase separation of the two compounds and the forming of ex-tended nanocrystalline Ge layers at 650°. These layers show a luminescence signal at 2.5 eV, which is contributed to defect luminescence.

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