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The impact of very thin sidewall LDD spacers which are required to allow sub-pm gate/space pitches on MOSFETs is discussed for the first time. The effects of LDD spacer materials, LPCVD TEOS and nitride, on the device characteristics and short channel behavior of n and p-channel MOSFETs are analyzed. We show that the main issue related to sub-100nm spacers is gate-induced drain leakage and not device reliability. Nitride spacers improve device reliability and current drive but result in higher levels of gate-induced drain leakage. Our findings show that for sub-half pm devices, spacer thickness reduction down to 600A has no appreciable effect on lifetime.

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AbsttactAn advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61prrP with conventional 1-line lithography and 7.32pm2 with 1-line phaseshift lithography. The process features PELOX isolation to provide a 1 .Opm active pitch, MOSFET transistors designed for a 0.80p.m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thinfilm polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance. IntroductionFast. hiah density static RAMS rewire both a small bitcell area an( a high'performance piocess. At thel6Mb generation, a bitcell area of less than 9.Op.rn2 can be achieved using 1-line technology with multiple layers of polysilicon and self-aligned contacts. Use of phase-shift lithography provides for even smaller bitcell areas. A symmetrical split word-line bitcell and thin film polysilicon transistors serve to enhance cell stability. Speed requirements can be met by adding a high performance, double polysilicon bipolar transistor. With careful design, bipolar parasitic capacitances can be even further reduced without increasing process complexity. With the aggressive scaling of bitcell areas at the 4Mb generation and beyond, SER has become a primary reliability concern for SRAMs. In this technology, a quadruple-well has been developed to provide diode isolation for the memory array while allowing for simultaneous optimization of MOSFETs and bipolars.