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Single-event effect (SEE) and total ionizing dose (TID) test results are presented for various hardened and commercial power metal-oxide-semiconductor field effect transistors (MOSFETs), including vertical planar, trench, superjunction, and lateral process designs. Index Terms-power MOSFET, single-event effect (SEE), single-event gate rupture (SEGR), single-event burnout (SEB), total ionizing dose (TID) I. INTRODUCTION OWER MOSFETs continue to be used ubiquitously in spacecraft. Several topologies are available. Planar, vertical double-diffused MOSFET (VDMOS) structures (Fig. 1A) have long dominated the radiation-hardened offerings, and the number of manufacturers providing hardened VDMOS has recently expanded. Commercially, vertical trench-gate style MOSFETs (Fig. 1B) have been a staple for low-to medium-voltage applications due to their lower on-state resistance (R DS_ON). The vertically-oriented gates penetrate past the body region thereby eliminating the parasitic junction field effect transistor (JFET) that limits the minimum cell pitch in planar VDMOS. For higher-voltage power MOSFETs, a lower R DS_ON has been achieved through development of the superjunction structure (Fig. 1C). Superjunction power MOSFETs (SJ MOSFETs) have charge-compensating columns within the epilayer that permit a shallower drift region for a given breakdown voltage (BV DSS). Radiationhardened SJ MOSFETs have just become available in the past year and hardened trench-style MOSFETs are in development.