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The need to support various digital signal processing (DSP)and classification applications on energy-constrained devices has steadily grown. Such applications often extensively perform matrix multiplications using fixed-point arithmetic while exhibiting tolerance for some computational errors. Hence, improving the energy efficiency of multiplications is critical. In this paper, we offer a similar speed, but with energy efficiency. The method is to collect the armature close to the closest momentum of two. An integral part of the computer, so the multiplication is eliminated, improving the speed and power consumption at a small error value. The proposed approach is to apply both signed and neglected. We offer three hardware implementations of an approximate multiplier that includes not being signed and signed for both operations. The effectiveness of this proposed multiplier is estimated by comparing its effectiveness with certain approximate and real-world by using different design parameters. In addition, the effect of the proposed approximate multipliers is examined in two applications for image processing, namely sharpness of the image. Keywords-Approximate multiplier, Energy efficiency and Power consumption ,integrated circuits, DSP I. BACKGROUND Energy minimization is one of the main design requirements in almost any electronic systems, especially the portable ones such as smart phones, tablets, and different gadgets [1]. It is highly desired to achieve this minimization with minimal performance (speed) penalty [1]. Therefore, improving the speed and power/energy-efficiency characteristics of multipliers plays a key role in improving the efficiency of processors. Many of the DSP cores implement image and video processing algorithms where final outputs are either images or videos prepared for human consumptions. This fact enables us to use approximations for improving the speed/energy efficiency. This originates from the limited perceptual abilities of human beings in observing an image or a video. In addition to the image and video processing applications, there are other areas where the exactness of the arithmetic operations is not critical to the functionality of the system (see [3], [4]). Being able to use the approximate computing provides the designer with the ability of making tradeoffs between the accuracy and the speed as well as power/energy consumption [2], [5]. Applying the approximation to the arithmetic units can be performed at different design abstraction levels including circuit, logic, and architecture levels, as well as algorithm and software layers [2]. The approximation may be performed

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