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In this paper, we introduce a fast and accurate 3D thermal analysis methodology for sequential face-to-back (F2B) and parallel face-to-face (F2F) 3D integration technologies. Our proposed models take design floorplan and the corresponding power map with temperature-dependent leakage power component and accurately estimate the temperature of any given location in the design. We show that our models are within less than 1% of commercial-grade finite-volume models while they are 100X faster. In addition, we demonstrate the minimum power reduction required in mobile 3D-ICs to achieve similar thermal behaviour of that of the corresponding 2D-ICs. Subsequently, we provide guidelines on 3D partitioning / floorplanning to further improve thermal profile of 3D-ICs.

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