This paper presents an improved approach to Triple Modular Redundancy (TMR) which concerns don’ t care bits of LUT configuration bits and hence classifies the set of LUTs into SEU-sensitive and SEU-insensitive. Unlike the full TMR approach, the improved approach only triplicates SEU-sensitive LUTs and can greatly reduces the area overhead while maintaining the circuit reliability. The proposed approach is thoroughly tested on the MCNC’91 benchmarks. Compare with the full TMR method the proposed scheme can reduce the area overhead by 26.6% on average, at the same time the circuit reliability only reduced by 9.1 %. The improved approach can also increase mean time between failures (MTBF) by an average of six times more than the original circuit.

In this paper a two-dimension BIST compression scheme is presented; the proposed scheme is utilized in order to drive down the number of deterministic vectors to achieve complete fault coverage in BIST applications. By introducing shifting compression and input reduction, vertical and horizontal compression are realized respectively to achieve two-dimension BIST compression. Experimental results show that the BIST shifting compression based on input reduction can achieve great compression rate as much as 99%. Comparisons with previously competitive presented schemes indicate that the proposed scheme provide an efficient BIST compression approach with lower storage overhead.