No abstract

Nanosheet (NS) vertical‐stacked complementary field‐effect transistors (CFETs), where the NS n‐FET and NS p‐FET are vertically stacked and controlled using a common gate, would result in maximum device footprint reduction. However, silicon‐based transistor will become invalid due to mobility degradation and leakage current rising when scaling the thickness of channel and dielectric. Here, it is experimentally demonstrated that CFET can scaling down to 1 nm channel thickness with excellent performance, where chemical vapor deposition (CVD) one layer (1L) WSe2 p‐type NS FET is vertically stacked on top of CVD 1L MoS2 n‐type NS FET. Bottom MoS2 NS FET achieves high on‐state current of ION = 3.3 × 10−5 A µm µm−1 and low off‐state current of IOFF = 3.3 × 10−13 A µm µm−1 at VDS = 0.7 V, with the subthreshold swing reaching 80 mV dec−1. Top WSe2 NS FET achieves high on‐state current of ION = 1.2 × 10−5 A µm µm−1 and IOFF = 4 × 10−11 A µm µm−1 at VDS = −0.7 V, while the subthreshold swing reaching 150 mV dec−1. Statistical data of 22 CFET devices demonstrate excellent uniformity toward large‐area applications. The CFET based on large‐scale 2D materials breaks the limit of channel scaling and provides a technological base for future high‐performance and low‐power electronics.