A sub-2Ops silicon bipolar technology has been developed using Selective Epitaxial Growth (SEG) for the active base and collector regions. This transistor concept allows the simultaneous reduction of base width and base/collector capacitance while maintaining low extrinsic base resistance.At a current of 0.8 mA a record CML gate delay time of 18ps is achieved with devices showing a cut-off frequency of 44 GHz. The high-speed capability of this technology has also been shown by a static 2:l frequency divider operating up to 25 GHz.