A new approach, micro benchmarks, has recently been developed. Using this technique, we have analyzed the KSR1, and in particular the "ALLCACHE" memory architecture and ring interconnection. We have been able to elucidate many facets of memory performance. The technique has enabled us to identify and characterize parts of the memory design not described by Kendall Square Research. Our results show that a miss in the local cache can incur a penalty ranging from 7.5 microseconds to 500 microseconds (when a dirty "page" in the local cache must be evicted). The programmer must be very careful in placement and accessing of data to obtain maximum performance from the KSR 1; the data presented here will help in understanding the performance actually obtained. The MicroBenchmark ApproachRecently, one of us (Saavedra) has explored a new approach to benchmark analysis of computers. This approach has been documented in several papers [11,12,13]. The approach was $

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Most Prolog machines have been based on specialized atchitecturns. Our goal is to start with a general purpose architecture and determine a minimal set of extensions for high performance Prolog execution. We have developed both the architecture and optimizing compiler simultaneously, drawing on results of previous implementations. We hnd that most Prolog specific operations can bc done satisfactorily in software: however, there is a crucial set of features that the architecturc must support to achieve the best Prolog performance. The emphasis of this paper is on our architecture and instruction set. The costs and benefits of the special architecturaI features and instructions are analyzed. Simulated perfonmmce results are presented and indicate. a peak compiled Prolog pcrformancc of 3.68 million logical inferences per second.

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