Background:After diagnosis, a substantial number of people with HIV disease fall out of care. Effective interventions are needed for this priority population.Methods:The “Peers Keep It Real” study aimed to help adults who were disengaged from HIV treatment. Peers, lay individuals living with HIV, facilitated intervention sessions. Participants were randomized to immediately receive the peer-facilitated intervention or were wait-listed.Results:Considerable attrition occurred in the control group. Pre-/postanalyses showed that among participants (n = 23) who received the intervention, 65% had viral load suppression and 100% remained in care at 12 months postintervention. Impact on viral load was significant (P = .0326), suggesting that peers are effective change agents who positively impacted outcomes for individuals struggling with adherence to HIV treatment.Conclusion:Future endeavors should consider providing all individuals from this priority population with an active peer intervention from the onset to enhance retention and adherence.

This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes.Index Terms-Automatic test pattern generation, cell-aware test, defect-based test, defective parts, design for testability, failure analysis, FinFET test, logic testing, test data compression, transistor-level test.

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This paper describes a new approach for significantly improving overall defect coverage for CMOS-based designs. We present results from a defect-oriented cellaware (CA) library characterization and patterngeneration flow and its application to 1,900 cells of a 32-nm technology. The CA flow enabled us to detect cell-internal bridges and opens that caused static, gross-delay, and small-delay defects. We present highvolume production test results from a 32-nm notebook processor to which CA test patterns were applied, including the defect rate reduction in PPM that was achieved after testing 800,000 parts. We also present cell-internal diagnosis and physical failure analysis results from one failing part.