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SUMMARYThis study considers a set of n rectangles arranged on a plane, and, in particular, the problem of modifying the initial layout within a minimum area while meeting certain conditions, namely, preservation of orthogonal order and prevention of intersection between rectangles. A heuristic algorithm for this problem with O(n 2 ) complexity was proposed by Misue and colleagues. First, the problem of minimum-area layout adjustment is shown to be NP-complete. Then, another heuristic algorithm is examined that results in smaller layout area than that of Misue and colleagues. Using computational experiments with random initial layouts, the proposed algorithm is proven to require 15 to 20% of the area required by the Misue algorithm, especially with a large number of rectangles.

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This paper presents a novel failure prediction technique that is applicable for system-on-chips (SoCs). Highly reliable systems such as automobiles, aircrafts, or medical equipments would not allow any interruptive erroneous responses during system operations, which might result in catastrophes. Therefore, we propose a failure prediction technique that can be applied during an idle time when a system is not working, such as power-on/-off time. To achieve high reliability in the field, the proposed technique should take into consideration various types of aging mechanisms and the testing environment of voltage and temperature which is uncontrollable in the field. Therefore, we propose: 1) an accurate delay measurement technique considering the variation due to voltage and temperature and 2) an adaptive test scheduling that gives more test chances to more probable degrading parts. Experimental results show the required memory space and area cost for implementing the proposed technique.