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International audienceConvolution is an important operation in image processing applications, such as edge detection, sharpening , adding blurring and so on. Convolving video streams in real-time is a challenging task for PC systems, however, FPGA devices can successfully be used in these tasks. In this article, the design and implementation of a reconfigurable FPGA architecture for 2D-convolution filtering is described. The filtered frames are calculated at a rate of 103 frames per second for images up to 1200×720 pixel resolution. By using a shift-based arithmetic and circular buffers, the developed FPGA architecture allows to reduce the hardware resources consumption up to 98% compared to the conventional convolution implementations , provides high speed processing and enables to manage large number of different convolution kernels. On the other hand, by using the CAPH language it is possible to reduce the design time up to 75% compared to the plain VHDL design. Furthermore, to maintain high flexibility in concordance with the input video, the developed hardware allows to configure the resolution of the input images with values of 3 × Y up to 1200 × Y , and allows scalability for different sizes of convolution kernels of simple and systematic form. Finally , the developed FPGA architecture for the proposed method was implemented and validated in an FPGA Cyclone II EP2C35F672C6 embedded in an Altera development board DE2

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Image processing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of silicon area. A field-programmable-gate-array- (FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this paper. The architecture is based on a 2D systolic array of configurable window processors. The architecture was implemented on an FPGA to execute algorithms with window sizes up to , but the design is scalable to cover larger window sizes if required. The architecture reaches a throughput of GOPs at a 60 MHz clock frequency and a processing time of milliseconds for generic window-based operators on gray-level images. The architecture compares favorably with other architectures in terms of performance and hardware utilization. Theoretical and experimental results are presented to demonstrate the architecture effectiveness.