Satellite backbone networks provide a viable means of establishing broadband connectivity for remote, sparsely populated areas. In addition, satellite communication systems are well suited for airborne, maritime, and disaster relief environments. Technologies for links are continuing to improve in performance and power efficiency, making onboard regeneration and routing feasible within spacecraft power envelope. In this article, we implement and analyze a spaceborne router design integrated on a field-programmable gate array (FPGA). FPGA provides a flexibility needed to circumvent space radiation effects on chip circuitry, as they can be reconfigured at runtime. We explored scalability of the high-end state-of-the art FPGA chip family, and its ability to support high bit-rate satellite links: 10 Gbps satellite-to-ground links and 100 Gbps intersatellite links. Through implementation and testing, we confirm that the current FPGA technology can support space routers with very high data throughput.

Shortest path algorithms for different applications, such as Internet routing, VLSI design and so on are used. Dijkstra and Bellman-Ford are commonly used shortest path algorithms which are typically implemented in networks with hundreds of nodes. However, scale of shortest path problems is increasing, and more efficient algorithms are needed. With the development of multicore processors, one natural way to speedup shortest path algorithms is through parallelization. In this paper, we propose a novel shortest path algorithm with parallel vertex transversal, and compare its speed with standard solutions in datacenter topologies.

-Performance of software routers is limited by the speed of the operating system network protocol stack. A faster network protocol stack can be implemented in user space by utilizing parallelization and different optimization techniques.In this work we demonstrate an efficient implementation of the IP lookup algorithm in user space with multibit trie structures. Afterwards, we demonstrate the improvements achieved through parallelization. We evaluate pthreads and OpenMP parallelization methods and compare their performance.

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