This paper presents a circuit optimization flow with a logic synthesis tool in a situation where register transfer level (RTL) false paths are given. RTL false path information can be utilized to obtain a more optimized circuit in logic synthesis. It is important to consider which RTL false paths are useful in logic synthesis so that an optimized circuit can be synthesized efficiently. The characteristics of such effective RTL false paths are analyzed from synthesis results in preliminary experiments. On the basis of the analysis, this paper formulates the problem of selecting RTL false paths and proposes a solution for it. Experimental results show that the proposed false path selection algorithm is effective in reducing area, delay and synthesis time compared with several possible false path selection methods.Index Terms-Logic synthesis, register transfer level false path, false path selection, area and delay optimization.