In this paper, we talk about techniques to incrementally resynthesize logic cones within a large design impacted by multiple RTL changes in order to accommodate a late functional ECO. In design methodologies where the RTL is hierarchical and the post route netlist is flat, mapping a change in the behavioral description to the post layout netlist is very complicated and may not even be feasible if the RTL is not written in a synthesis friendly manner. We try to attack this problem by introducing a technique that causes minimum perturbation to the gate level netlist, thereby retaining to a large degree, the goodness metrics of timing convergence, routability and layout cleanliness that were achieved during the various design milestones. This paper talks about the cone resynthesis ECO methodology in detail and highlights its usefulness during tight product deliverable schedules.