We report on a highly compact, one diode-one resistor (1D-1R) nanopillar device architecture for SiOx-based ReRAM fabricated using nanosphere lithography (NSL). The intrinsic SiOx-based resistive switching element and Si diode are self-aligned on an epitaxial silicon wafer using NSL and a deep-Si-etch process without conventional photolithography. AC-pulse response in 50 ns regime, multibit operation, and good reliability are demonstrated. The NSL process provides a fast and economical approach to large-scale patterning of high-density 1D-1R ReRAM with good potential for use in future applications.

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This study investigates the electrical instability under negative gate bias stress (NGBS) induced by surface hydrolysis effect. Electrical characteristics exhibit instability for amorphous InGaZnO (a-IGZO) Thin Film Transistors (TFTs) under NGBS, in which on-current degradation and current crowding phenomenon can be observed. When the negative gate bias is applied on the TFT, hydrogen ions will dissociate from ZnO-H bonds and the dissociated hydrogen ions will cause electrical instability under NGBS. The ISE-Technology Computer Aided Design simulation tool and moisture partial pressure modulation measurement are utilized to clarify the anomalous degradation behavior.

Co nanodot memory devices formed by oxidation processes were studied. Transmission electron microscopy and x-ray photoelectron spectroscopy analyses showed that overoxidation of the cobalt and silicon degraded the charge-storage ability seriously. However, a precapped oxide can mildly oxidize the CoSi 2 film to protect the overoxidation to occur. In addition, an oxygen-incorporated CoSi 2 film is proposed to improve the oxidation process further. Through incorporating the limited oxygen during sputtering process, the Co nanodot memory device obtains a larger memory window. Also, the reliability characteristic of the Co nanodot memory device formed by annealing the oxygen-incorporated CoSi 2 film has been demonstrated.

We propose a method to fabricate a Ni nanocrystal structure by simultaneously coevaporating Ni and SiO 2 pellets. An 800°C rapid thermal annealing was used to enhance the Ni nanocrystals to aggregate. Transmission electron microscopy indicates that the formed Ni nanocrystals show a high density distribution of about 4.5 ϫ 10 12 cm −2 . Then, the memory device using the Ni nanocrystals as charge-trapping centers was fabricated. The Ni nanocrystal memory device has an obvious memory window under capacitance-voltage measurement. X-ray photoelectron spectroscopy confirms the memory effect results from the Ni nanocrystals embedded in the SiO 2 dielectric layer. Moreover, related reliability characteristics have been extracted.Recently, a nanocrystal ͑NC͒ structure is considered for application in several electrical devices, including nonvolatile memory, photodetector, or single-electron transistor. 1-3 In the nonvolatile memory devices, a distributed NC structure can provide correct judgment for the logic circuit even if a leakage path is formed in the tunneling oxide. 4 In the major topic of an NC device, the uniformity and density of NCs are the critical problems in replacing the conventional floating-gate memory structure. Based on these reasons, several NC fabricating methods have been investigated to improve the NC performance, such as atomic layer deposition, pulsed-laser deposition, and in situ annealing processes. 5-7 Among the reported processes, ion implantation has also been studied to fabricate a high density NC structure. 8,9 However, the implantation to fabricate the NC structure is difficult to combine with the current memory device fabricating technology due to the consideration of tunneling oxide damage.In this article, a method was proposed to fabricate a Ni NC structure by simultaneously coevaporating Ni and SiO 2 pellets. After a thermal annealing process, a high density of Ni NC distribution of about 4.5 ϫ 10 12 cm −3 was observed by the cross-section and plane-view transmission electron microscopy ͑TEM͒ results. Then, the reasonable NC formation process has been studied and demonstrated. Related material analyses confirm that the formed structure consists of the Ni NCs embedded in SiO 2 . Moreover, the Ni NCs formed by annealing the coevaporated film have been implanted into the metal-oxide-insulator-oxide-silicon ͑MOIOS͒ structure to study the memory effect. The Ni NC memory device has an excellent charge-storage ability, including memory window, retention, and endurance characteristics. ExperimentalThe memory structure was fabricated on a 6 in. p-type Si substrate. First, a 5 nm thick SiO 2 was grown as the tunneling oxide by dry oxidation in an atmospheric pressure chemical vapor deposition furnace. Then, a dual electron-gun ͑E-gun͒ system was used to deposit the charge-trapping layer of the device. In the codeposition process, Ni and SiO 2 pellets were placed in their respective crucibles. Subsequently, an approximately 10 nm thick mixed film composed of Ni and SiO 2 was deposited by coevapor...