A lower power consumption, smaller output ripple and better regulation boost power converter controlled by voltage feedback and pulse-width modulation (PWM) mode is implemented in this paper. The over-current protection and soft-start circuit can produce a slowly rising output voltage without extra clock or any external component to prevent inrush current and output voltage overshoot during the start-up period of the converter. The converter is designed and simulated using the TSMC 0.35μm 2P4M CMOS Process. Hspice simulation results show that, the boost converter having chip size with power efficiency about . This chip can operate with input supply voltage from to , and its output voltage can stable at and less than ripple voltage at maximum loading current . The simulation shows the circuit has about of soft-start time and can inhibit the inrush current when the power on.

This paper proposes a low power bandgap reference voltage circuit that provides an output reference voltage close to the bandgap voltage having a low output resistance and allows resistive loading. This proposed circuit is design and implemented using the TSMC 0.18μm 1P6M CMOS process. Simulation and measured results verify that the chip size is with power dissipation about 0.1mW, and the operation temperature range formwith temperature coefficient about . The chip supply voltage can from 1.3 to 1.8V with PSRR about 70 dB, and its output reference voltage can stable on .

A lower power consumption, smaller output ripple and better regulation buck dcdc converter controlled by voltage feedback and pulse-frequency modulation (PFM) mode is implemented in this paper. The converter operating in discontinuous conduction mode (DCM) is designed and simulated using the TSMC 0.18μm 1P6M CMOS Process. Hspice simulation results show that, the buck converter having chip size with power dissipation about 0.68mW. This chip can operate with input supply voltage from 1.2V to 1.8V, and switching frequency from 249KHz () to 50KHz (), and its output voltage can stable at 1.0V and less than 110mV ripple voltage at maximum loading current 100 mA.

This paper proposes a low bandgap reference voltage circuit with low temperature coefficient and independent of suply voltage for applications to power management IC. This proposed circuit is design and implemented using the TSMC 0.35μm CMOS 2P4M process. Based on simulated and measured results , the chip size is 20.6000.680mm with power dissipation about 3.3mW, and the operation temperature range form 0Cto 100C with temperature coefficient about 9.29/ppmC. The chip suply voltage can from 2.9V to 3.3V with PSRR about 44.2 dB, and its output reference voltage can stable at 0.65V.

As the progress with all kinds of mixed-mode signal circuits, the requirements of power management become increasingly stringent. Therefore it takes all kinds of high-performance linear regulator to produce a very clean and stable voltage. Here cascading technique is used to increase the output impedance in this architecture. The output voltage is less susceptible to variation of input voltage, resulting in a clean and stable voltage which is used the operating voltage of internal circuits in a mixed-mode signal integrated circuit chip. This paper using the TSMC 0.35μm CMOS 2P4M process to implement the design of high PSRR LDO regulator, having chip area, 1.34 mW consumption power. The chip supply voltage can from 2.9V to 3.3V with -106dB and -65dB PSRR at 1KHz and 100KHz, and its output voltage can stable at 1.2V and less than 2.4mV ripple voltage at maximum loading current 20 mA.