Flexibility and programmability of hearing aids are important because the algorithms applied to hearing aids should be changeable based on different types of hearing impairment and the ambient environment of the user. This paper proposes a high-performance digital signal processing (DSP) platform for a digital hearing aid system on a chip (SoC) with flexible noise estimation. The proposed DSP platform comprises several dedicated accelerators and an application-specific instruction-set processor (ASIP) to achieve flexibility. To handle complex hearing aid algorithms in real time, the main algorithms of hearing aids are executed by hardware accelerators and only environment-sensitive parts of the applied algorithms are implemented as the ASIP. Simulation results show that the proposed DSP platform can handle complex and high-performance algorithms in real time, and that it provides better quality in terms of noise handling by adapting the noise estimation algorithms suitable for the noise environment. The chip area of authors' DSP design is 2.71 mm 2 , and it consumes 1.3 mW at 1 V operation, 8 MHz clock frequency with a 65 nm high threshold voltage (HVT) standard cell library. 2 Proposed DSP platform Our design is focused on achieving high performance and user customisation under the constraints of hearing aids, such as lowpower consumption and real-time operation. The hardware block diagram and operational flow of the DSP platform proposed here are illustrated in Figs. 1 and 2, respectively. The 32-bit DSP