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This paper presents a new spatio-temporal motion estimation algorithm for video coding. The algorithm is based on optimization theory and consists of the strategies including 3D spatio-temporal motion vector prediction, modified one-at-a-time search scheme, and multiple update paths. The simulation results indicate our algorithm is better than other recently proposed ones under the same computational budget and is very close to full search. The low-cost feature and regular demand of computational resource make our algorithm suitable for VLSI implementation. The algorithm also makes single chip solution for high-definition coding feasible.

Based on concurrent exploration of both algorithm and architecture, this paper introduces an efficient verification methodology that targets at comprehensive functional verification throughout different levels of design granularities for multi-format media SoC's with applications in MPEG's Reconfigurable Video Coding. We present a verification technique that minimizes the number of test patterns but at the same time covering multiple profiles based on the functional commonalities extracted from multiple coding standards. In addition, algorithmic complexity analysis and dataflow modeling are also used to gain insight into flexible video architecture at early design stage in facilitating more efficient verification environment. Furthermore, an isolation technique is also presented for independent verification of coarse grain modules in the system level. We have shown that this verification methodology can effectively enhance the reliability and efficiency of SoC's with high complexity and reconfigurability.

This paper presents a unified systolic architecture for inter and intra predictions in H.264/AVC decoder. To increase hardware utilization and minimize cost, we combine inter and intra predictions by a reprogrammable FIR filter, which is further implemented using systolic array. For intra prediction, the boundary pixels are reshuffled before feeding into the systolic array. For inter prediction, the 2-D interpolation is conducted through separable 1-D filtering. As compared with the state-of-the-art approaches, our architecture provides higher performance while maintaining relatively lower cost and input bandwidth. Specifically, up to 4x throughput improvement has been achieved. Moreover, the input bandwidth is significantly reduced. Further, combining inter and intra predictions saves the cost by 22∼88%.

In this paper, a novel edge pattern recognition (EPR) deinterlacing algorithm with successive 4-field enhanced motion detection is introduced. The EPR algorithm surpasses the performance of ELA-based and other conventional methods especially at textural scenes. In addition, the current 4-field enhanced motion detection scheme overcomes conventional motion missing artifacts by gaining good motion detection accuracies and suppression of "motion missing" detection errors efficiently. Furthermore, with the incorporation of our new successive 4-field enhanced motion detection, the interpolation technique of EPR algorithm is capable of flexible adaptation in achieving better performance on textural scenes in generic video sequences.