In this paper, a design for high dynamic range applicable of power detector by using successive detection logarithmic amplifier (SDLA) configuration consists of PMOS load limiting amplifier and unbalanced sourcecoupled pairs. This device was been fabricated by TSMC 0.18-μm 1P6M CMOS process. The experimental results show that the dynamic range of the power detector the frequency 900-MHz is almost kept at 39-dB and for frequency 1800-MHz, the dynamic range is 29-dB. Its logerror is kept at ±1-dB and consumes is 16-mW from a 1.8-V supply.Index Terms-successive detection logarithmic amplifier, SDLA, power detector, power control, limiting amplifier, unbalanced source-coupled pairs

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