Economic dispatch problem (EDP) is a fundamental optimization problem in power system operation, which aims at minimizing the total generation cost. In fact, the power grid is becoming a cyber-physical power system (CPPS). Therefore, the quality of communication is a key point. In this paper, considering two important factors, i.e., time delays and channel noises, a fully distributed consensus based algorithm is proposed for solving EDP. The critical maximum allowable upper bounds of heterogeneous communication delays and self-delays are obtained. It should be pointed out that the proposed algorithm can be robust against the time-varying delays and channel noises considering generator constraints. In addition, even with time-varying delays and channel noises, the power balance of supply and demand is not broken during the optimization. Several simulation studies are presented to validate the correctness and superiority of the developed results.

A novel magnetic ion exchange resin called MIEX Resin is being utilized in potable water treatment, which indicates significant advantages. The objective of this article is to analyze characteristics and application of MIEX Resin in engineering projects, and hence provide critical review on merits and demerits of the resin. Furthermore, researches on combination of MIEX Resin with other water treatment technologies would be analyzed and discussed to prove potential that a MIEX Resin process integrated with other treatments can be employed in broader fields of wastewater treatment and reuse.

Background: Recording of electrical activity of neurons is indispensable for decoding the information in the brain. The amplitude of signals recorded by electrodes is small, and it must be amplified to the level that can be digitalized by the analog-to-digital convert (ADC). A micro-power low-noise neural recording amplifier is indispensable for implant hippocampal cognitive prosthesis. When the process turns into deep submicron, the gate leakage current of the metal oxide semiconductor (MOS) transistor becomes larger and mismatch between devices becomes worsen. It is necessary to keep the neural amplifier robust in all process corners. Methods: The proposed circuit is a two-stage amplifier which can achieve a good trade-off between power consumption and noise. Four second-stage amplifiers share a common reference amplifier to reduce area and power consumption. A pseudo-resistor with high resistance is utilized to realize a very-low frequency high pass corner without external components. In order to minimize process variation, a bulk-compensated (BC) technique is adopted to maintain adequate tolerance in all corner case. Results: The 4-channel neural amplifier is designed and fabricated in a 40 nm standard complementary metal oxide semiconductor (CMOS) process. It achieves a mid-band gain of 54 dB, a bandwidth of 70 Hz to 7.7 kHz, a total input-referred noise of 3.2 μVrms , and a Noise Efficiency Factor (NEF) of 3.3 while consuming 4.68 µW from the 1.1 V supply. The core area of one channel is only 0.032 mm 2 . Conclusion: A 4-channel integrated neural recording amplifier chip with bias-compensated circuits is presented in this paper. Extensive simulations insure that the design is “center”. The chip layout is verified using design rules check (DRC) and layout versus schematic (LVS) design check with the help of verification tools. Test results shows that it is less sensitive to process variation and consumes less power compared with amplifier without bulk-compensated circuit. This makes the design robust and uniquely appropriate for low-power implant application.

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