No abstract

This paper presents a phase-locked loop (PLL) with a novel phase frequency detector (PFD) and charge pump (CP) which can extend the linear phase difference detection range and eliminate cycle slips. Thus, the frequency settling time can be effectively reduced compared with the conventional PFD and CP during the frequency acquisition process. The proposed PLL with linear range extension PFD and CP (LEPFD/CP) is designed in 180 nm BiCMOS technology and occupies 3.61 mm 2 area. As the LEPFD/CP is disabled when the PLL is locked, the PLL is robust enough and the extra power consumption can be ignored. The measurement results show that a 50 MHz reference frequency acquisition process with 10 μs has been accelerated 3.7 times compared with the conventional PFD/CP PLL with the same 200 kHz loop bandwidth.