Different from the traditional quaternary tree (QT) structure utilized in the previous generation video coding standard H.265/HEVC, a brand new partition structure named quadtree with nested multi-type tree (QTMT) is applied in the latest codec H.266/VVC. The introduction of QTMT brings in superior encoding performance at the cost of great time-consuming. Therefore, a fast intra partition algorithm based on variance and Sobel operator is proposed in this paper. The proposed method settles the novel asymmetrical partition issue in VVC by well balancing the reduction of computational complexity and the loss of encoding quality. To be more concrete, we first terminate further splitting of a coding unit (CU) when the texture of it is judged as smooth. Then, we use Sobel operator to extract gradient features to decide whether to split this CU by QT, thus terminating further MT partitions. Finally, a completely novel method to choose only one partition from five QTMT partitions is applied. Obviously, homogeneous area tends to use a larger CU as a whole to do prediction while CUs with complicated texture are prone to be divided into small sub-CUs and these sub-CUs usually have different textures from each other. We calculate the variance of variance of each sub-CU to decide which partition will distinguish the sub-textures best. Our method is embedded into the latest VVC official reference software VTM-7.0. Comparing to anchor VTM-7.0, our method saves the encoding time by 49.27% on average at the cost of only 1.63% BDBR increase. As a traditional scheme based on variance and gradient to decrease the computational complexity in VVC intra coding, our method outperforms other relative existing state-of-the-art methods, including traditional machine learning and convolution neural network methods. INDEX TERMS Asymmetric block size, fast partition decision, intra prediction, quadtree with multi-type tree, versatile video coding YIBO FAN received the B.E. degree in electronics and engineering from

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Network on chip (NoC) architecture is viewed as a potential solution for the interconnect demands of the emerging multi-core systems since it renders the system high performance, flexibility and low-cost. Mapping tasks onto different cores of the network is a critical phase in NoC design because it determines the energy consumption and packet latency. In order to reduce the energy consumption of applications running on multi-core architecture, we propose a new mapping strategy based on Simulated Annealing (SA). By allocating tasks that have big communication volume to adjacent places on the mesh, the proposed method overcomes the shortcoming of blind search in traditional SA. The experiment results reveal that the solutions generated by the proposed algorithm reduce average energy consumption by 56.56% in mapping 16 tasks and 66.32% in mapping 49 tasks compared with traditional Simulated Annealing (SA). I