Abstract-The orthogonal signal generator based phase-locked loops (OSG-PLLs) are among the most popular single-phase PLLs within the areas of power electronics and power systems, mainly because they are often easy to be implement and offer a robust performance against the grid disturbances. The main aim of this paper is to present a survey of the comparative performance evaluation among the state-of-the-art OSG-PLLs (include Delay-PLL, Deri-PLL, Park-PLL, SOGI-PLL, DOEC-PLL, VTD-PLL, CCF-PLL, and TPFA-PLL) under different grid disturbances such as voltage sags, phase and frequency jumps, and in the presence of dc offset, harmonic components, and white noise in their input. This analysis provides a useful insight about the advantages and disadvantages of these PLLs. The performance enhancement of Delay-PLL, Deri-PLL, and CCF-PLL by including a moving average (MAF) filter into their structure is another goal of this paper. . His research interests include phase-locked loop (PLL), AC/DC microgrids, power quality, grid-connected converters for renewable and DGs, active power filters and static synchronous compensators (STATCOMs). He has authored more than 20 ISI-indexed journal papers in the area of power electronics, power quality conditioners, and smart grid. He received Best Paper

The moving average filter (MAF) is widely utilized to improve the disturbance rejection capability of phase-locked loops (PLLs). This is of vital significance for the grid-integration and stable operation of power electronic converters to electric power systems. However, the open-loop bandwidth is drastically reduced after incorporating a MAF into the PLL structure, which makes the dynamic response sluggish. To overcome this shortcoming, some new techniques have recently been proposed to improve the transient response of MAF-based PLLs. In this paper, a comprehensive performance comparison of advanced MAFbased PLL algorithms is presented. This comparison includes HPLL, MPLC-PLL, QT1-PLL, and DMAF-PLL. Various disturbances, such as grid voltage sag, voltage flicker, harmonics distortion, phase-angle and frequency jumps, DC offsets and noise, are considered to experimentally test the dynamic performances of these PLL algorithms. Finally, an improved positive sequence extraction method for a HPLL under the frequency jumps scenario is presented to compensate for the steady-state error caused by non-frequency adaptive DSC, and a satisfactory performance has been achieved.

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