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Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.

We propose a top-down hardwarelsoftware co-simulation method for embedded systems and introduce a component logical bus architecture as an interface between software components and hardware components. CO-simulation using a component logical bus architecture is possible in the same environment from the stage at which the processor is not yet determined to the stage at which the processor is modeled in register transfer language. A model whose design is based on a component logical bus architecture is replaceable and reusable. By combining such replaceable models, it is possible to quickly realize seamless co-simulation. We further describe experimental results of our approach. I . In.troduction As semiconductor technology advances into deepsubmicron areas, high-performance processors (microprocessors, DSPs, etc.) have begun to appear. As a result, functions which had previously been realized exclusively in hardware circuitry have come to be implemented in software, and it is now possible to design electronic products as embedded systems, combining hardware and software.Particdarly in the development of multimedia products, it has become necessary to combine flexible software with high-performance hardware as a means of exploring new markets and responding promptly to user needs and as a means of reducing product development cycles.Hardwarelsoftware co-design techniques are now attracting attention as one means of reahzing embedded systems. There have been numerous studies [1]-[5] on: hardwarelsoftware partitioning, suzuki@dpe.mdl.melco.co.jp * hardwarelsoftware co-synthesis, and hardwarelsoftware co-simulation.In the fkst stage of the top-down design, the a r c h i t e m and algorithm of the target system are evaluated. Then, the embedded system is partitioned into hardware components and software components.These components are first modeled at an abstract level and are evaluated by co-simulation. These models are then subsequently replaced by detaded models.In order to realm seamless co-simulation in the top down design flow, it is necessary to d e h e the interface between the hardware components and the software components and the modeling methods of hardware components and software components.Two methods for modeling hardware, software and the interface between themthe virtual CPU approach [I * the channel-based component architecture [6], --have been reported. In the channel-based component architecture, the interfaces between components and their operation are s p e d e d to achieve co-synthesis at the system level. In the virtual CPU approach, a CPU model and its interface to other components are d e h e d to r e h a co-simulation environment.We propose an efficient top-down approach of co-simulation for embedded systems in which upper models are replaced successively by lower detailed models.By introducing a component logical bus architecture as the interface between hardware components and software components, this method provides an environment for co-simulation which does not depend on processor and s...

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