In this paper we show how to translate bounded-length verification problems for timed automata into formulae in difference logic, a propositional logic enriched with timing constraints. We describe the principles of a satisfiability checker specialized for this logic that we have implemented and report some preliminary experimental results.

We propose models that capture the influence of computation on the performance of computer-controlled systems, and make it possible to employ computational considerations in early stages of the design process of such systems. The problem of whether it is possible to meet performance requirements given resource constraints is phrased as a problem of synthesizing switching controllers for hybrid automata, for which we give algorithms that in some cases are guaranteed to terminate and in others can solve the problem in an approximate manner.