The objective of this research is to design and develop a flexible programmable video coprocessor. The processor targets applications for MPEG2 format. Five basic processing tasks have been identified as the main job of the coprocessor. They contribute to a wide variety of operations frequently needed by multimedia applications. These tasks are frame rate conversion (increase of frame rate or decrease of frame rate), resolution conversion, changing bits per pixel, filtering, and video compositing operations (rotations or mirroring of frame). The first phase of this project 1 presented a critical comprehensive study of the algorithms capable of performing these tasks in the DCT domain. In this paper the details of coprocessor design, implementation and the simulation of the chip are presented.