In this article, we survey existing academic and commercial efforts to provide Field-Programmable Gate Array (FPGA) acceleration in datacenters and the cloud. The goal is a critical review of existing systems and a discussion of their evolution from single workstations with PCI-attached FPGAs in the early days of reconfigurable computing to the integration of FPGA farms in large-scale computing infrastructures. From the lessons learned, we discuss the future of FPGAs in datacenters and the cloud and assess the challenges likely to be encountered along the way. The article explores current architectures and discusses scalability and abstractions supported by operating systems, middleware, and virtualization. Hardware and software security becomes critical when infrastructure is shared among tenants with disparate backgrounds. We review the vulnerabilities of current systems and possible attack scenarios and discuss mitigation strategies, some of which impact FPGA architecture and technology. The viability of these architectures for popular applications is reviewed, with a particular focus on deep learning and scientific computing. This work draws from workshop discussions, panel sessions including the participation of experts in the reconfigurable computing field, and private discussions among these experts. These interactions have harmonized the terminology, taxonomy, and the important topics covered in this manuscript.

Hardware Trojan horses (HTHs) are malicious inclusions or alterations to hardware designs developed and supplied by untrusted parties. The emerging threat of HTHs has a direct impact on the FPGA design community which mainly relies on third-party IP (3PIP) cores and design reuse practices. Efficient design and detection of HTHs have been the main interest of most related research work, but countermeasures against HTHs have not attained sufficient attention. We advance a novel approach promoting Smart Employment of Circuit Redundancy to Effectively Counter Trojans (SECRET) in 3PIP cores employed in reconfigurable hardware designs. Two identical instances of the protected IP core are employed for observation and operating purposes and a time shift is created between the two core inputs. Trojan detection circuitry is inserted during the design-time to monitor the observation core at run-time. Once a Trojan is detected in the observation core, the operating core with the delayed input is suspended or the identified triggering inputs are isolated for a specific period of time to bypass the Trojan activating trigger. We present the SECRET high-level architecture, a proof-of-concept application to a 3PIP crypto core containing an HTH of our design. The prototype is designed and validated on a Spartan-3 FPGA. Simulation and implementation results show the SECRET feasibility and effectiveness.

Datacenters of today have maintained the same architecture for decades. The building block of the datacenter remains the server, which tightly couples the necessary compute resources, memory, and storage to run its tasks. However, this traditional approach suffers from under-utilization of its resources, often caused by the over-provisioning of these resources when deploying applications. Datacenter operators allocate the worst-case amount of memory required for each deployed application, which lasts for the entirety of the application's lifetime, even when not actually used. This causes servers to quickly, and falsely, run out of memory before their CPUs have been fully utilized. To address these problems, a new shift in the way datacenters are being built has been gaining more traction. Namely, memory disaggregation. Memory disaggregation can address these problems by decoupling the computational elements from the memory resources, allowing each to be provisioned and utilized separately. While the idea of memory disaggregation is not new, an increasing number of different proposals of memory disaggregation have seen the light in recent years. In this paper, we review many of these recent proposals, and study their architectures, implementations, and requirements. We also categorize them based on their features, and attempt to identify their strengths and shortcomings in an effort to highlight possible directions for future work and provide a reference for the research community.

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