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Feature extraction is an important function in the speech recognition system. Employing a speech recognition system in low-resource devices (LRDs) have increased significantly in recent years. Implementing feature extraction, which involves complex computations, in LRD is very challenging because LRD has limited energy, storage, and processing power. The optimum design must carefully balance performance metrics, including speed, area, and energy. The objective of this research is to implement and model speech feature extraction design in a field-programmable gate array (FPGA) platform, and to identify the optimum implementation for low-resource devices (LRDs). The novelty of this research is optimising feature extraction implementations using design options such as word size; and developing accurate performance models to enhance future designs. The authors study extensively examines the effect of fixed-point n-bit word size on the design of Mel frequency cepstral coefficients feature extraction in the FPGA implementation. The results show that the performance metrics (area, power, and energy) increase at a slower pace compared with n because the dependency of some blocks (e.g. logarithm) on n is non-linear. For example, increasing n by 50% increases the resource utilisation by 38%, power by 41% and energy by 41%. Models for resources, power, and energy are developed with accuracies of 5.1, 4.5, and 4.3%, respectively. Furthermore, n has a weak impact on timing results and therefore speed is almost similar across implementations. Each bit (in n) costs 690 logical elements in the area, 2.35 mW in power and 0.55μJ in energy. For LRD, the 32-bit design demonstrates the most optimum design, followed by 48-bit and 24-bit designs.

Abstract-The Process Network (PN) model consists of multiple concurrent processes communicating over a unidirectional First-In-First-Out (FIFO) queue. Process networks are widely used for functional parallelism in digital signal processing and streaming data applications such as MPEG encoding and decoding. However, the bounded-memory scheduling policy of process networks can lead to process deadlock. The current deadlock detection and recovery algorithms in process networks can be enhanced by incorporating the role of a coordinator.In this paper we propose an enhanced distributed deadlock detection and recovery algorithm using blocked-lists and a coordinator to detect and recover from deadlocks. The distributed blocked-list algorithms detect the blocked processes and merge them with the existing blocked-lists. When a cycle is detected in the blocked-list, the coordinator is invoked to recover the system from the deadlock by either increasing the size of the channel for artificial deadlocks or by terminating the lowest priority processes from the blocked-lists. Our evaluation of the algorithm shows that the proposed blocked-list algorithm out performs other algorithms by requiring fewer messages to detect and recover from deadlock.Index Terms-Deadlock detection, deadlock recovery, distributed systems, kahn process networks (KPN).

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