Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

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With the widespread adoption of the internet of things (IoT), power management of the different electronic (i.e. IoT) devices has become a major challenge. The low-dropout linear regulator (LDO) circuit is widely used for power management applications of electronic devices. This article reports the design and simulation of a low-dropout linear regulator (LDO) circuit, powered by a 1.2 V DC power supply voltage. In order to optimise the power dissipation, low layout silicon area and lower dropout voltage, a current mirror based transistor optimised LDO circuit has been implemented. The simulation results show that the proposed LDO regulator circuit exhibits a 582 mV low-dropout voltage, 1.568 mW power dissipation, and a very compact layout silicon area of 163.84 µm 2(12.795 × 12.805 µm). The proposed LDO linear regulator archi- tecture is designed and validated in 0.13 µm TSMC CMOS process technology using Mentor Graphic EDA tools.

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