Abstract:The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in -parallel out (PIPO) and serial in -serial out (SISO) shift register respectively covering 22 µm 2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.

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Level Shifter (LS) circuits are widely used as interfaces for multiple voltage domains in moderns ICs and System on Chips (SoCs). Low power dissipation and low delay are the main design considerations for high performance level shifters. This paper presents the design of a level shifter integrating new topological modifications to assure a wide range of voltage conversion with low power dissipation and low output delay. The presented level shifter is designed to take input signal of 1 V and convert that into an output signal of 1.8 V which is simulated in Silterra 0.13 µm CMOS process. The post layout simulation results show that the designed LS circuit has a significant low power dissipation of only 0.1449 nW and low output delay of 25.55 ps covering only 17.36× 14.560 µm2 chip area. Through detailed comparison with recently reported LS circuits, it has been shown that the proposed level shifter achieved a better performance in terms of power consumption, delay and compact chip size.