As threshold voltage of CMOS transistors is the main parameter that takes effect from process variations, in this paper a novel method for corner detection is presented which senses the variations of fabrication process through threshold voltage of the devices. A new general purpose 2-input, 2-output, 25 rules, ANFIS based fuzzy controller is proposed to compensate the variations subsequently. In this controller novel structures are presented for each block including membership function generator, Min-Max selector and defuzzifier. As an application, bias points of comparators of a typical flash ADC are controlled through introduced system in order to compensate the process variation effects and minimizing total power consumption consequently. Due to differential structures used in the architecture of the blocks, major part of the power supply noise is rejected. The Hspice (level 49) simulation results are given using a generic 0.35 lm standard CMOS technology parameters and power supply of 3.3 V with total power consumption of 15.6 mW for 7.4 MFLIPS. Because of simple and symmetrical circuitry, layout of the proposed controller is very compact, about 410 lm 9 210 lm.

Unlike the twisted pair cable's simple installation mechanism, evaluating a circuit equivalent and certifying it is not very convenient anymore. Although the best way to model transmission lines is to use the field solver software programs such as ANSYS Maxwell or HFSS, this procedure is very overwhelming and time-consuming. This paper presents a straightforward approach to extract a W-element model for the twisted pair cable based on its structural and electrical characteristics. The W-element model employs a novel state-of-the-art transmission line simulation method which is very fast, accurate and robust. Both system designers and cable manufacturers can easily exploit the presented equations and the derived models to predict the behavior of the balanced transmission lines with two conductors using simulators such as HSpice, etc. Nexans unshielded CAT6 twisted pair cable, one of the most common types of cables used in today's networks, is selected as a case study in this paper to verify the proposed model. A variety of simulations have been carried out to evaluate the performance and accuracy of the proposed model. Furthermore, the validity of the model is assessed against the real Fluke test results. INDEX TERMS Twisted pair cable, W-element, Transmission line modeling, Fluke test, RLGC model. I. NOMENCLATURE ε 0 Permittivity of free space ε r Relative permittivity of material µ0 Magnetic permeability of free space µr Relative magnetic permeability of material ρ Specific electrical resistance of material σ DC conductivity of the insulation material δ Skin depth f Frequency d Diameter of the conductor D Center to center separation of the conductors H Height of the wire above the ground NVP Nominal Velocity of Propagation tan(δ) Loss tangent of insulation material kp Correction factor of proximity effect l Length of wire lmax Maximum length of RLGC element LCable Cable jacket length Lwire Wire's electrical length Lwire-pitch Wire's pitch length

Predicting MOSFET models plays a pivotal role in circuit design and its optimization. Independent Gate FinFETs (IGFinFET) are interesting for designers as they are more flexible than Common Multi-Gate FinFETs (CMGFinFET) in digital circuit design. In this work, we implement a model for symmetrical IGFinFET using CMGFinFET model based on Multi-Gate Predictive Technology Model (PTM-MG). This model has been developed from TCAD IGFinFET, based on previously published experimental results of CMGFinFET. Different basic gates in SG (shorted gate), LP (low power), IG (low area), and IG/LP modes have been designed using the implemented model. For LP, IG, and IG/LP NAND gates, the leakage power is reduced by 89%, 26%, and 67%, respectively in comparison to SG. To show that our model does not have any convergence problem for large circuits, we used ISCAS'85 benchmark suite. The results show that for independent gate in high performance PTM-MG library, on average we can save up to 24% in the number of transistors and lower the total power by 42%

This paper presents a new adaptive prioritization and fail-over mechanism for ring network adapters (RNA). Owing to the use of a shared medium in the structure of ring networks, management of network resources is very important and cannot completely be fulfilled by fixed priority strategies. An adaptive prioritization mechanism for efficient utilization of network resources is proposed in this paper. Hop-Count and the distance between source and destination are the key parameters that are included in the priority assignment procedure. Unlike the conventional ones, the arrived traffic is not put blindly into the queues thanks to the awareness of stations form status of each other. The newly introduced fail-over mechanism is based on the Power over Ethernet concept. Each station monitors the heartbeat of its neighbors and tries to keep them alive by providing their minimum required electrical power whenever a fault occurs. By doing so, not only single failure but also any successive double failure scenarios cannot disrupt data path continuity. Several simulations are carried out to assess the behavior and performance of the proposed methods in OPNET Modeler. Moreover, a high-speed USB test board is designed using Xilinx-Spartan6-lx9 FPGA to experimentally verify the performance of the proposed mechanisms. INDEX TERMS Ring network, weighted fair queuing, node failure, fail-over mechanism, power over Ethernet.

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